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THS8083APZP 数据表(PDF) 8 Page - Texas Instruments |
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THS8083APZP 数据表(HTML) 8 Page - Texas Instruments |
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8 / 64 page  1–2 • Output Formatter – Single and double pixel width output data bus for reduced board clock frequency and EMI – Support for 4:4:4 and 4:2:2 (ITU–R BT.601 style) output modes to reduce board traces – Dedicated DATACLK output for easy latching of output data • System – Industry-standard normal/fast I2C interface with register readback capability – Support for input format detection via integrated monitoring of HS, VS, and pixel clock frequencies – Support for multidevice operation (master/slave operation for SXGA resolution) – Space-saving TQFP-100 pin package – Thermally-enhanced PowerPAD package for better heat dissipation • Applications – LCD desktop monitors and LCD or DMD-based projection systems – Videoconferencing – PCTV set-top boxes, digital TV sets, and multimedia cards – Scan rate/image resolution converters – Video/graphics digitizing equipment (RGB or YUV-based) |
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