ADE9078 datasheet(65/108 Pages) AD

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ADE9078

Data Sheet

Rev. 0 | Page 64 of 107

After the SS line is set high by master, the ADE9078 stops driving

MISO and enables a 100 kΩ weak pull-up. It is recommended to

have the SCLK line idle high. An example of a SPI burst read

operation is given in Figure 97, when BURST_EN = 1. For other

examples, see the Burst Read Waveform Buffer Samples from

SPI section.

SPI PROTOCOL CRC

The ADE9078 SPI port calculates a 16-bit cyclic redundancy

check (CRC-16) of the data sent out on its MOSI pin so that the

integrity of the data received by the master can be checked. The

CRC of the data sent out on the MOSI pin during the last

appended to the SPI read data as part of the SPI transaction.

The CRC_SPI register value is appended to the 16-/32-bit data

read from the register addressed in the CMD_HDR for the cases in

Table 25 where CRC is written (see the SPI Read section for

more information).

The CRC result can always be read from the CRC_SPI register

directly.

There is no CRC checking as part of the SPI write register protocol.

To ensure the data integrity of the SPI write operation, read the

correctly.

CRC Algorithm

The CRC algorithm implemented within the ADE9078 is based

on the CRC-16 CCITT algorithm. The data output on MISO is

introduced into a linear feedback shift register (LFSR) based

generator one byte at a time, MSB first without bit reversal, as

shown in Figure 101 and Figure 102. The 16-bit result is written

in the CRC_SPI register.

LFSR

GENERATOR

a31

MISO 32-BIT DATA

815

Figure 101. CRC Calculation of 32-Bit SPI Data

a15

LFSR

GENERATOR

MISO 16-BIT DATA

Figure 102. CRC Calculation of 16-Bit SPI Data

LFSR

g15

b15

a31, a30, ..., a2, a1, a0

Figure 103. LFSR Generator Used for CRC_SPI Calculation

Figure 103 shows how the LFSR works. The MISO 32-bit data

forms the [a31, a30, …, a0] bits used by the LFSR. Bit a0 is Bit 31 of

the first MISO 32-bit data to enter the LFSR, whereas the last

data to enter the LFSR, Bit a31, corresponds to Bit 0 transmitted

on MISO. The formulas that govern the LFSR are as follows:

bi(0) = 1, where i = 0, 1, 2, …, 15, the initial state of the bits that

form the CRC. Bit b0 is the LSB, and Bit b15 is the MSB.

gi, where i = 0, 1, 2, …, 15 are the coefficients of the generating

polynomial defined by the CRC-16 CCITT algorithm as

follows:

G(x) = x16 + x12 + x5 + 1

(1)

g0 = g5 = g12 = 1

(2)

All other gi coefficients are equal to 0.

FB(j) = aj − 1 XOR b15(j − 1)

(3)

b0(j) = FB(j) AND g0

(4)

bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, …, 15

(5)

Equation 3, Equation 4, and Equation 5 must be repeated for j =

1, 2, …, 32. The value written into the CRC_SPI register contains

Bit bi(32), i = 0, 1, …, 15.

A similar process is followed for 16-bit data (see Figure 102 for

information about how the bits are ordered into the LFSR).

ADDITIONAL COMMUNICATION VERIFICATION

REGISTERS

The ADE9078 includes three registers that allow SPI operations

to be verified. The LAST_CMD (Address 0x04AE, LAST_

DATA_16 (Address 0x4AC), and LAST_DATA_32

(Address 0x423) registers record the received CMD_HDR and

last read/transmitted data. The LAST_DATA_16 register

contains the last data read or written during the last 16-bit

transaction, whereas the LAST_DATA_32 holds the data read

or written during the last 32-bit transaction.

The LAST_CMD register is updated after the CMD_HDR is

received. Note that the three LSBs of LAST_CMD always reads

back as 000. Also note that if a command to read the LAST_CMD,

LAST_DATA_16, or LAST_DATA_32 registers is received,

these three registers are not updated.

During a SPI read operation, LAST_DATA_16 and LAST_DATA_32

are updated within two master clocks after the CMD_HDR is

received.

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