ADE9078 datasheet(96/108 Pages) AD

96 / 108 page

Data Sheet

ADE9078

Rev. 0| Page 95 of 107

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

REVAPA

Set this bit to enable an interrupt when the Phase A

total active power has changed sign.

0x0

R/W

EGYRDY

Set this bit to enable an interrupt when the power

values in the xWATTHR, xVAHR, xVARHR, and

xFVARHR registers have been updated, after

EGY_TIME 4 kSPS samples or line cycles,

depending on the EGY_TMR_MODE bit in the

EP_CFG register.

0x0

R/W

0x406 MASK1

ERROR3

Set this bit to enable an interrupt if ERROR3

occurs. Issue a software reset or hardware reset to

clear this error.

0x0

R/W

ERROR2

Set this bit to enable an interrupt if ERROR2

occurs.

0x0

R/W

ERROR1

This interrupt is not maskable. Issue a software

reset or hardware reset to clear this error.

0x0

R/W

ERROR0

This interrupt is not maskable. Issue a software

reset or hardware reset to clear this error.

0x0

R/W

CRC_DONE

Set this bit to enable an interrupt when the

configuration register CRC calculation is done,

after initiated by writing the FORCE_CRC_UPDATE

bit in the CRC_FORCE register.

0x0

R/W

CRC_CHG

Set this bit to enable an interrupt if any of the

registers monitored by the configuration register

CRC change value. The CRC_RSLT register holds

the new configuration register CRC value.

0x0

R/W

[25:19] RESERVED

Reserved.

0x0

SEQERR

Set this bit to set an interrupt when on a phase

sequence error on the phase voltage zero

crossings.

0x0

R/W

[17:16] RESERVED

Reserved.

0x0

ZXIC