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ADE9078 数据表(PDF) 85 Page - Analog Devices |
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ADE9078 数据表(HTML) 85 Page - Analog Devices |
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85 / 108 page  ADE9078 Data Sheet Rev. 0 | Page 84 of 107 Addr. Name Description Len (Bits) Reset Access 0x487 ANGL_VC_IC Time between positive to negative zero crossings on Phase C voltage and current. 16 0x0000 R 0x488 ANGL_IA_IB Time between positive to negative zero crossings on Phase A and Phase B current. 16 0x0000 R 0x489 ANGL_IB_IC Time between positive to negative zero crossings on Phase B and Phase C current. 16 0x0000 R 0x48A ANGL_IA_IC Time between positive to negative zero crossings on Phase A and Phase C current. 16 0x0000 R 0x490 CFMODE CFx configuration register. 16 0x0000 R/W 0x491 COMPMODE Computation mode register. 16 0x0000 R/W 0x492 ACCMODE Accumulation mode register. 16 0x0000 R/W 0x493 CONFIG3 Configuration Register 3. 16 0x0000 R/W 0x494 CF1DEN CF1 denominator register. 16 0xFFFF R/W 0x495 CF2DEN CF2 denominator register. 16 0xFFFF R/W 0x496 CF3DEN CF3 denominator register. 16 0xFFFF R/W 0x497 CF4DEN CF4 denominator register. 16 0xFFFF R/W 0x498 ZXTOUT Zero-crossing timeout configuration register. 16 0xFFFF R/W 0x499 ZXTHRSH Voltage channel zero-crossing threshold register. 16 0x0009 R/W 0x49A ZX_LP_SEL This register selects which zero crossing and which line period measurement are used for other calculations. 16 0x001E R/W 0x49C SEQ_CYC Number of line cycles used for phase sequence detection. It is recommended to set this register to 1. 16 0x00FF R/W 0x49D PHSIGN Power sign register. 16 0x0000 R 0x4A0 WFB_CFG Waveform buffer configuration register. 16 0x0000 R/W 0x4A1 WFB_PG_IRQEN This register enables interrupts to occur after specific pages of the waveform buffer have been filled. 16 0x0000 R/W 0x4A2 WFB_TRG_CFG This register enables events to trigger a capture in the waveform buffer. 16 0x0000 R/W 0x4A3 WFB_TRG_STAT This register indicates the last page that was filled in the waveform buffer and the location of trigger events. 16 0x0000 R/W 0x4A4 CONFIG5 Configuration Register 5. 16 0x0063 R/W 0x4A8 CRC_RSLT This register holds the CRC of configuration registers. 16 0x0000 R 0x4A9 CRC_SPI This register holds the 16-bit CRC of the data sent out on the MOSI pin during the last SPI register read. 16 0x0000 R 0x4AC LAST_DATA_16 This register holds the data read or written during the last 16-bit transaction on the SPI port. 16 0x0000 R 0x4AE LAST_CMD This register holds the address and read/write operation request (CMD_HDR) for the last transaction on the SPI port. 16 0x0000 R 0x4AF CONFIG2 Configuration Register 2. 16 0x0C00 R/W 0x4B0 EP_CFG Energy and power accumulation configuration. 16 0x0000 R/W 0x4B1 PWR_TIME Power update time configuration. 16 0x00FF R/W 0x4B2 EGY_TIME Energy accumulation update time configuration. 16 0x00FF R/W 0x4B4 CRC_FORCE This register forces an update of the CRC of configuration registers. 16 0x0000 R/W 0x4B5 CRC_OPTEN This register selects which registers are optionally included in the configuration register CRC feature. 16 0x0000 R/W |
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