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ADE9078 数据表(PDF) 23 Page - Analog Devices |
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ADE9078 数据表(HTML) 23 Page - Analog Devices |
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23 / 108 page ![]() ADE9078 Data Sheet Rev. 0 | Page 22 of 107 THEORY OF OPERATION The ADE9078 integrates seven high performance ADCs and a flexible DSP core. An integrated high end reference ensures low drift over temperature with a combined drift of less than ±25 ppm/°C maximum for the whole channel including PGA and ADC. The ADE9078 is a highly accurate, fully integrated energy metering device. Interfacing with both CT and Rogowski coil sensors, the ADE9078 enables users to develop a 3-phase metrology platform, which achieves high performance for Class 1 through Class 0.2 meters. See the Measurements (Normal Mode) section for more information. Two power modes are provided to enable detection of meter tampering: PSM2 uses a low power comparator to compare current channels to a threshold and indicates whether it has been exceeded on the IRQ0 and IRQ1 outputs; PSM1 enables fast measurement of current and voltage rms (xVRMS, xIRMS), active power, and VAR during a tamper. See the Measurements (PSM1) section and Measurements (PSM2) section for more information about how to use these modes. ADC Overview The ADE9078 incorporates seven independent, second-order, Σ-Δ ADCs that sample simultaneously. Each ADC is 24 bits and supports fully differential and pseudo differential inputs that can go above and below ground. The ADE9078 includes a low noise, low drift, internal band gap reference. Set the EXT_REF bit in the CONFIG1 register if using an external voltage reference. Each ADC contains a programmable gain amplifier, which allows a gain of 1, 2, or 4. The ADCs incorporate proprietary dither techniques to prevent idle tones at low input levels, extending the accuracy range. Analog Input Configuration There is no internal buffering on the device. The impedance of the ADE9078 depends on the programmable gain selected (see the Specifications table). Fully Differential Inputs The input signals on the IAP, IAN, IBP, IBN, ICP, ICN, VAP, VAN, VBP, VBN, VCP, and VCN pins must not exceed 0.6 V relative to AGND, the analog ground reference. The differential full- scale input range of the ADCs is ±1 V peak (0.707 V rms), and the maximum allowed common-mode voltage at the ADC pins must not exceed ±0.1 V. Figure 30 and Figure 31 show two common types of input signals for an energy metering application. Figure 30 shows the maximum input allowed with differential antiphase signals. A current transformer with center tapped burden resistor generates differential antiphase signals. Figure 31 shows the maximum input signal with pseudo differential signals, similar to those obtained when sensing the mains voltage signal through a resistive divider or using a Rogowski coil current sensor. The following conditions must be met for the input signals with gain = 1: |IAP, IAN, IBP, IBN, ICP, ICN, VAP, VAN, VBP, VBN, VCP, and VCN| ≤ 0.6 V peak relative to AGND |IxP − IxN| ≤ 1 V peak, |VxP − VxN| ≤ 1 V peak +0.1V 0 +0.6V –0.4V 0x0474 E650 = NOTES 1. x_PCF IS THE INSTANTANEOUS WAVEFORM OBTAINED AFTER GAIN AND PHASE COMPENSATION. +74,770,000 0xFB8B 19B0 = –74,770,000 CHANNEL (x_PCF) WAVEFORM DATA RANGE WITH x_GAIN = 1 xP INPUT PIN xM INPUT PIN +0.1V +0.6V –0.4V Figure 30. Maximum Input Signal with Differential Antiphase Input with Common-Mode Voltage = 0.1 V, Gain = 1 +0.1V 0 +0.6V –0.4V +0.1V 0x0474 E650 = +74,770,000 xFB8B 19B0 = –74,770,000 CHANNEL (x_PCF) WAVEFORM DATA RANGE WITH x_GAIN = 2 xP INPUT PIN xM INPUT PIN NOTES 1. x_PCF IS THE INSTANTANEOUS WAVEFORM OBTAINED AFTER GAIN AND PHASE COMPENSATION. Figure 31. Maximum Input Signal with Pseudo Differential Input with Common-Mode Voltage = 0.1 V, Gain = 2 Each ADC contains a programmable gain amplifier that allows a gain of 1, 2, or 4. The ADC produces full-scale output codes with an input of ±1 V. With a gain of 1, this full-scale input corresponds to a differential antiphase input of 0.707 V rms, as shown in Figure 30. At a gain of 2, full-scale output codes are produced with an input of 0.353 V rms, as shown in Figure 31. At a gain |
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