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ADE9078 数据表(PDF) 28 Page - Analog Devices |
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ADE9078 数据表(HTML) 28 Page - Analog Devices |
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28 / 108 page ![]() Data Sheet ADE9078 Rev. 0 | Page 27 of 107 Reset If the RESET pin goes low for 1 μs, the AVDD and DVDD LDOs turn off. The power on sequence resumes from the point where the AVDD and DVDD LDOs are turned on (see the Power-On Sequence section for details). A software reset is initiated by writing the SWRST bit in the CONFIG1 register, which resets the digital logic and takes ~60 μs to complete. For applications that require putting the ADE9078 into a low power mode, it is recommended to use PSM3. In this mode, the ADE9078 consumes approximately 2 μA, much lower than the 100 μA current consumption obtained when the ADE9078 RESET pin is held low (see Table 1 for the exact PSM3 current consumption). Changing to PSM2 or PSM3 The state of the PM1 and PM0 pins is continuously monitored. If the power mode changes from PSM0 or PSM1 to PSM2 or PSM3 (PM1, PM0 = 10 or 11) for 1 μs, the AVDD and DVDD LDOs are turned off. When the power mode switches back to PSM0 or PSM1, the power on sequence resumes from the point where AVDD and DVDD LDOs are turned on (see the Power- On Sequence section for details). MEASUREMENTS (NORMAL MODE) The ADE9078 offers per phase total IRMS and VRMS as well as total active power, VAR, VA, and fundamental VAR powers. The instantaneous low-pass filtered powers can be accumulated into power or energy registers and are available in pulsed outputs, CF1 through CF4. Power quality information, such as zero-crossing detection, line period, and angle measurements, is also available. A waveform buffer stores samples directly from the ADC, calculated resampled data, or processed current and voltage samples. The measurements described are available in PSM0, the normal operating mode. A reduced set of features is available in PSM1 and PSM2 (see the Power Modes section for more details on these operating modes). SINC4 AND DECIMATION AVDD LDO DVDD LDO SPI 1.25V REFERENCE TEMP SENSOR CF1 TO CF4 IRQ0 IRQ1 SPI PM1 PM0 ADE9078 PGA ADC PGA ADC SAR AVAILABLE IN PSM0 AVAILABLE IN PSM2 DISABLED IN PSM1 PGA ADC PGA ADC PGA ADC PGA ADC PGA ADC METROLOGY FEATURES (PER PHASE) IRMS, VRMS ACTIVE POWER, VA YX, ANGLE WAVEFORM BUFFER ENERGY/POWER/CF ACCUMULATION LINE FREQUENCY ETC. LOW POWER COMPARATOR Figure 40. Features Available in Each Operating Mode Current Channel The current channel datapath for IA, IB, and IC is shown in Figure 41. The current channel ADC waveforms can be sampled at the sinc4 output in the xI_SINC_DAT registers at 16 kSPS, or further decimated by an IIR low-pass filter in the xI_LPF_DAT registers at 4 kSPS. Gain and phase compensation are applied, creating the xI_PCF instantaneous current waveforms that update at 4 kSPS. The xI_PCF waveforms are used for total active power, VAR, IRMS, VA, and fundamental VAR calculations. The xI_PCF value is also monitored in the current peak detection circuit. The rms of the sum of instantaneous currents measurement uses the AI_PCF, BI_PCF, and CI_PCF current channel waveforms to calculate the neutral current or ro calculate the net vector current sum including the neutral current measurement, NI_PCF (see the Neutral Current RMS, RMS of Sum of Instantaneous Currents section for more information). Finally, the angle measurements indicate the time between the current channel zero crossing and the voltage channel zero crossing on the same phase or current channels on the other phases, updating at 512 kSPS in the ANGLx_x registers. The neutral current channel, Channel IN, offers a neutral current sum rms and is used in an rms of instantaneous current measurement, as shown in Figure 42. For more information about these calculations, see the Neutral Current RMS, RMS of Sum of Instantaneous Currents section. Channel IN offers a gain calibration (NIGAIN) and a phase calibration (NPHCAL). The digital integrator on Channel IN is enabled by setting the ININTEN bit in the CONFIG0 register. Note that the Channel IN neutral current modulator is turned off in PSM1. |
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