ADE9078 datasheet(27/108 Pages) AD

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ADE9078

Data Sheet

Rev. 0 | Page 26 of 107

Table 8. Power Modes (PSM0, PSM1, PSM2, and PSM3)

PSMx

Power

Mode

Description

PM1

PM0

Power

Consumption

Functions Available

SPI

Available

Retained Registers

When Switching into

Power Mode

PSM0

Normal mode

10 mA

All functions.

Yes

Not applicable

PSM1

Tamper

measurement

mode

9 mA

Active and reactive power, IRMS, VRMS, all

calculated using the PSM1 computation method.

ZX, period, and angle measurements are available.

The neutral current channel, waveform buffer, and

energy/power/CF accumulations are disabled.

Yes

Not applicable

PSM2

Current peak

detect mode

115 µA

Current peak detect.

PSM2_CFG

PSM3

Idle

50 nA

None.

PSM2_CFG

Power-On Sequence

HOST CONFIGURES

IC VIA SPI AND THEN

WRITES RUN

MEASUREMENTS

20ms

0.5ms

~26ms

ADE9078

RSTDONE

INTERRUPT

TRIGGERED

CRYSTAL

OSCILLATOR

STARTS

POR TIMER

TURNED ON

AVDD, DVDD

LDO TURNED

POWER APPLIED

TO IC

IN PSM0, PSM1

Figure 39. Power-On Sequence for PSM0 and PSM1

After power is applied to the VDD pin of the ADE9078, the

device checks the state of the PM0 and PM1 pins to check the

power supply mode (see the Power Modes section for more

information). If in PSM1 or PSM0 (PM1, PM0 = 00 or 01) and

if the RESET pin is high, the AVDD and DVDD LDOs turn on

after VDD reaches 2.4 V to 2.6 V. If the RESET pin is low, the

AVDD and DVDD LDOs are not turned on. Note that a clamp

limits the current used to charge the AVDD and DVDD LDOs

to approximately 17 mA per LDO. The power supply source must

be able to handle approximate charge current of 40 mA.

When AVDD and DVDD are both above 1.3 V to 1.5 V and

VDD is above 2.4 V to 2.6 V, a 20 ms timer is started to allow

additional time for the supplies to reach their normal potentials

(VDD between 2.7 V and 3.6 V, AVDD at 1.9 V, and DVDD at

1.7 V). After this timer has elapsed, the crystal oscillator starts.

The RSTDONE interrupt is triggered approximately 26 ms later,

bringing the IRQ1 pin low and setting the RSTDONE bit in the

STATUS1 register. This RSTDONE interrupt indicates to the

user that the ADE9078 has finished its power-up sequence.

Then, the user can configure the IC via the SPI (see the Quick

Start section for a list of important registers to configure). After

configuring the device, write the run register to start the DSP so

that it starts making measurements. Note that registers from

Address 0x000 through Address 0x0FF and Address 0x400

through Address 0x5FF are restored to their default values

during power-on. Registers from Address 0x200 through

Address 0x3FF are cleared within 500 µs from when the run

the waveform buffer, Address 0x800 through Address 0xFFF, is

not cleared after reset.

In PSM2 and PSM3, the AVDD and DVDD LDOs are not

turned on. The RSTDONE interrupt does not occur and the SPI

port is not available (see the Power Modes section for more

information on these modes).

Brownout Detection

Power-on reset (POR) circuits monitor the VDD, AVDD, and

DVDD supplies. If AVDD or DVDD drop below a threshold

between 1.3 V and 1.5 V, or VDD drops below a threshold between

2.4 V and 2.6 V, the IC is held in reset. If the power-on sequence

begins again, the ADE9078 waits until AVDD and DVDD are

above 1.3 V to 1.5 V and VDD is above 2.4 V to 2.6 V to start

the 20 ms POR timer. A RSTDONE interrupt on the IRQ1 pin

indicates when the ADE9078 can be reinitialized via SPI.

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