ADE9078 datasheet(25/108 Pages) AD

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ADE9078

Data Sheet

Rev. 0 | Page 24 of 107

The output data rates are summarized in Table 7.

Table 7. Output Data Rates

Parameter

Data Rate

CLKIN Frequency

12.288 MHz

ADC Modulator Clock, MODCLK

1.024 MHz

Sinc4, SINC_ODR

16 kHz

Low-Pass Filter

4 kHz

Bandwidth (Pass Band)

0.672 kHz

The ADC data in the waveform buffer is stored as 32-bit data by

shifting left by 4 bits and sign extending, as shown in Figure 36.

ADC_DATA[23:0]

0000

Figure 36. Format for the ADC Data Stored in the Waveform Buffer,

x_SINC_DAT and x_LPF_DAT Registers

The expected output code from the sinc4 filter when input is at 1 V

peak is 4,190,000 decimal (d), which corresponds to a value of

67,110,000d in the waveform buffer. The expected output code

from the decimator filter when input is at 1 V peak is 4,660,000d,

which corresponds to a value of 74,520,000d in the waveform

buffer (see the Waveform Buffer section for more information).

Voltage Reference

The ADE9078 supports a 1.25 V internal reference. The

temperature drift of the reference voltage is ±5 ppm/°C typical,

±20 ppm/°C maximum. An external reference can be connected

between the REF and REFGND pins. Set the EXT_REF bit of

the CONFIG1 register when using an external voltage reference,

which disables the internal reference buffer.

CRYSTAL OSCILLATOR/EXTERNAL CLOCK

The ADE9078 contains a crystal oscillator. Alternatively, a digital

clock signal can be applied at the CLKIN pin of the ADE9078.

When a crystal is used as the clock source for the ADE9078,

attach the crystal and the ceramic capacitors, with capacitances

of CL1 and CL2, as shown in Figure 37. It is not recommended to

attach an external feedback resistor in parallel to the crystal.

When a digital clock signal is applied at the CLKIN pin, the

inverted output is available at the CLKOUT pin. This output is

not buffered internally and cannot drive any other external

devices directly. Note that CLKOUT is available in the PSM0

and PSM1 operating modes only.

CLKIN

CLKOUT

1.75kΩ

2.5kΩ

CIN1

CIN2

12.288MHz

Figure 37. Crystal Application Circuit

Crystal Selection

The transconductance of the crystal oscillator circuit in the

ADE9078, gm, is provided in Table 1. It is recommended to have

three to five times more gm than the calculated gmCRITICAL for the

crystal.

The following equation shows how to calculate the gmCRITICAL for

the crystal from information given in the crystal data sheet:

gmCRITICAL = 4 × ESRMAX × 1000 × (2π × fCLK(Hz))2 × (C0 + CL)2

where:

gmCRITICAL is the minimum gain required to start the crystal in mA/V.

ESRMAX is the maximum electrical series resistance (ESR),

expressed in Ω.

fCLK (Hz) is 12.288 MHz, expressed in Hz as 12.288 × 106.

C0 is the maximum shunt capacitance, expressed in farads.

CL is the total load capacitance, expressed in farads.

Crystals with low ESR and smaller load capacitance have a

lower gmCRITICAL and are easier to drive.

The evaluation board of the ADE9078 uses a crystal manufactured

by Abracon (ABLS-12.288MHZ-L4Q-T), which has a maximum

ESR of 50 Ω, a load capacitance of 18 pF, and a maximum shunt

capacitance of 7 pF, which results in a gmCRITICAL of 0.75 mA/V, as

follows:

gmCRITICAL = 4 × ESRMAX × 1000 × (2π × fCLK(Hz))2 × (C0 + CL)2

gmCRITICAL = 4 × 50 × 1000 × (2π × 12.288 × 106)2 × (7 ×

10−120+ 18 × 10−12)2 = 0.75 mA/V

The gain of the crystal oscillator circuit in the ADE9078, the gm,

provided in Table 1 is more than 5 × gmCRITICAL; thus, there is

sufficient margin to start up this crystal.

Load Capacitor Calculation

Crystal manufacturers specify the combined load capacitance

across the crystal, CL. The capacitances in Figure 37 can be

described as follows:



CP1 and CP2 are the parasitic capacitances on the clock pins

formed due to PCB traces.



CIN1 and CIN2 are the internal capacitances of the CLKIN

and CLKOUT pins, respectively.



CL1 and CL2 are the selected load capacitors to reach the

correct combined CL for the crystal.

The internal pin capacitances, CIN1 and CIN2, are 4 pF each, as

given in Table 1. To find the values of CP1 and CP2, measure the

capacitance on each of the clock pins of the PCB, CLKIN, and

CLKOUT, respectively, with respect to the AGND pin. If the

measurement is performed after soldering the IC to the PCB,

subtract the 4 pF internal capacitance of the clock pins to

determine the actual value of parasitic capacitance on each of the

crystal pins.

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