ADE9078 datasheet(72/108 Pages) AD

72 / 108 page

Data Sheet

ADE9078

Rev. 0 | Page 71 of 107

When the WF_CAP_EN bit is set, whichever mode selected by

the WF_CAP_SEL and WF_MODE bits in the WFB_CFG register

is initiated.

For example, if WF_CAP_SEL = 0, the resampled waveforms

are stored into the buffer. If WF_CAP_SEL = 1, the fixed data

rate samples are stored into the buffer, and the WF_MODE bits

indicate whether the buffer is filled continuously or only one

time, and if trigger events affects the buffer filling. All of these

bits must be configured before writing the WF_CAP_EN bit in

the WFB_CFG register.

When the waveform buffer is disabled by clearing the

WF_CAP_EN bit, the waveform buffer data remains valid;

however, the WFB_LAST_ADDR and WFB_TRIG_ADDR

registers are reset.

To start a new waveform capture, disable the waveform buffer

by writing WF_CAP_EN = 0. Then, configure the WF_CAP_SEL

and WF_MODE bits as desired by writing to the WFB_CFG

or WF_MODE bits while the WF_CAP_EN bit is set.

BURST READ WAVEFORM BUFFER SAMPLES

FROM SPI

The waveform buffer contents can be read using the SPI burst

read mode. The SPI burst read mode allows many samples of

data to be read while only sending one SPI command header.

To make it easier to read out the desired data using the SPI burst

read functionality, the user can indicate which channels of data

to read out of the waveform buffer, using the BURST_CHAN bits

in the WFB_CFG register, as shown in Table 29.

Table 29. Waveform Buffer Burst Read

BURST_CHAN

Channels to Burst

0000 (default)

All channels

0001

IA and VA

0010

IB and VB

0011

IC and VC

1000

1001

1010

1011

1100

1101

1110

IN if WF_IN_EN = 1 in the WFB_CFG

1111

Single address read (SPI burst mode is

disabled)

The same BURST_CHAN options are available for both fixed

data rate samples and resampled data.

The waveform buffer sample that is read out depends on the

selection in BURST_CHAN and whether the stored data is fixed

data rate data or resampled data.

If BURST_CHAN is not equal to 1111, and the fixed data rate

data is stored in the waveform buffer, when WF_CAP_SEL = 1,

the three LSBs of the address are masked out when determining

which sample set to read out.

If BURST_CHAN is not equal to 1111, and resampled data is

stored in the waveform buffer, when WF_CAP_SEL = 0, the

two LSBs of the address are masked out when determining

which sample set to read out.

If BURST_CHAN = 1111, whichever address was written in the

CMD_HDR is read out.

These cases are summarized in Table 30.

Table 30. SPI Address Interpretation when Reading from

Waveform Buffer

Address of Sample (Set)

Capture Type

BURST_CHAN ≠

1111

BURST_CHAN =

1111

Fixed Data Rate Samples

(WF_CAP_SEL = 1)

ADDR, Bits[11:3]

ADDR, Bits [11:0]

Resampled Data

(WF_CAP_SEL = 0)

ADDR, Bits

[11:2]

ADDR, Bits [11:0]

Example 1: Fixed Data Rate Data, Seven Channel

Samples

In this example, WFB_CAP_SEL = 1, WF_IN_EN = 1, and

BURST_CHAN = 0000 in the WFB_CFG register, which indicates

that there is fixed data rate data in the waveform buffer, and the

user wants to read out samples from all seven channels. A

command is sent to read Address 0x801, which is interpreted as

a read to the sample set starting at Address 0x800. The first 32

SPI clocks return IA from Address 0x800, followed by VA from

Address 0x801, and so on until IN returns from Address 0x806.

Then, the sample set auto-increments and the next data is IA

from Address 0x808, followed by VA. This example is depicted

in Figure 110.

Example 2: Resampled Data, Phase C (I and V Samples)

In this example, WFB_CAP_SEL = 0 and BURST_CHAN =

0011 in the WFB_CFG register, which indicates that there is

resampled data in the waveform buffer, and the user wants to read

out IC and VC samples. A command is sent to read Address 0x801,

which is interpreted as a read to the sample set starting at

Address 0x800. The first 16 SPI clocks return the IC waveform

from Address 0x802, followed by VC from Address 0x802.

Then, the sample set auto-increments and the next data is IC

from Address 0x806, followed by VC from the same address.

Then, IC from Address 0x80A and VC from Address 0x80A and

are read out. This example is depicted in Figure 111.

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