ADE9078 datasheet(24/108 Pages) AD

24 / 108 page

Data Sheet

ADE9078

Rev. 0 | Page 23 of 107

of 4, full-scale output codes are generated with a 0.1765 V rms

input signal. Note that the voltages on the xP and xN pins must

be within ±0.6 V as described in this section and Table 1.

Write the x_GAIN bits in the PGA_GAIN register to configure

the gain for each channel.

Interfacing to Current and Voltage Sensors

Figure 32 and Figure 34 show the typical circuits to connect to

current transformer and Rogowski coil current sensors. Figure 33

shows the typical interface circuit to measure the mains voltage.

The antialiasing filter corner is chosen to be around 7 kHz to

provide sufficient attenuation of out of band signals near the

modulator clock frequency. The same RC filter corner is used

on voltage channels, as well, to avoid phase errors between current

and voltage signals. Note that the Rogowski coil (that is, a di/dt

sensor) input network has a second-order antialiasing filter. The

integrator used in conjunction to the Rogowski coil has a

−20 dB/dec attenuation and an approximately −90° phase shift.

When combined with a di/dt sensor, the resulting magnitude

and phase response is a flat gain over the frequency band of

interest. However, the di/dt sensor has a 20 dB/dec gain associated

with it, and it generates significant high frequency noise. An

antialiasing filter of at least the second order is required to avoid

noise aliasing back in the band of interest when the ADC is

sampling. See Figure 34 for the recommended antialiasing filter.

1kΩ

8.2Ω

22nF

AGND

IxP

IxN

0.656V rms max

100A RMS MAX

10A RMS NOM

8.2Ω

1kΩ

22nF

AGND

2500:1

Figure 32. Application Circuit with a Current Transformer Current Sensor

1MΩ

1kΩ

22nF

AGND

VxP

VxN

0.240V rms

240V rms

1kΩ

22nF

NEUTRAL

PHASE

AGND

Figure 33. Application Circuit with Voltage Sensed Through Resistor Divider

1kΩ

IxP

IxN

0.3535V rms

22nF

100Ω

1kΩ

22nF

100Ω

Figure 34. Application Circuit with Rogowski Coil Current Sensor

Internal RF Immunity Filter

Energy metering applications require the meter to be immune to

external radio frequency fields of 30 V/m, from 80 MHz to 10 GHz,

according to IEC 61000-4-3. The ADE9078 has internal antialias-

ing filters to improve performance in testing because it is difficult

to filter these signals externally. The second-order, internal low-

pass filter has a corner frequency of 10 MHz. Note that external

antialias filters are required to attenuate frequencies above 7 kHz, as

shown in the Interfacing to Current and Voltage Sensors section.

Modes of Operation

Each ADC has two modes of operation: normal mode and

disabled mode.

In the normal mode, the ADCs turn on and sample continuously.

Use the CHNL_DIS register to disable the ADCs individually.

Four different power modes are available in the ADE9078 (see

the Power Modes section). All ADCs turn on during the PSM0

power mode. In the PSM1 power mode, all of the ADCs except for

the neutral current ADC are turned on. In PSM2 mode and

PSM3 mode, all ADCs are disabled and cannot be turned on.

Table 6. ADC Operation in PSMx Power Modes

PSMx Power Mode

ADC Mode of Operation

PSM0

Normal (on)

PSM1

IA, IB, IC, VA, VB, VC: normal (on)

IN: disabled (always off)

PSM2

Disabled (always off)

PSM3

Disabled (always off)

Output Data Rates and Format

When a conversion is complete, the DREADY bit of the STATUS0

are equal to 11, the CF4/EVENT/DREADY pin corresponds to

DREADY and pulses high to indicate when seven new ADC

results are ready. Note that the DREADY update rate depends

on the data selected in the WF_SRC bits in the WFB_CFG register.

For the ADE9078, the modulator sampling rate (MODCLK) is

fixed at 1.024 MHz (CLKIN/12 = 12.288 MHz/12). The output

data rate of the sinc4 filter is 16 kHz (SINC_ODR = MODCLK/64),

whereas the low-pass filter/decimator stage yields an output rate

four times slower than the sinc4 filter output rate (SINC_ODR).

Figure 35 shows the digital filtering, which takes the 1.024 MHz

ADC samples and creates waveform information at a decimated

rate of 16 kHz or 4 kHz.

ANALOG

INPUT

Σ-∆ × 7

DIGITAL

MULTIBIT

SINC4

IIR LPF/

DECIMATOR

DIGITAL

WAVEFORM

BUFFER

(×7 CHANNELS)

1.024MHz

16kHz

4kHz

Figure 35. Datapath Following ADC Stage

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