L3GD20H datasheet(18/52 Pages) STMICROELECTRONICS

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Digital main blocks

L3GD20H

18/52

DocID023469 Rev 2

Digital main blocks

4.1

Block diagram

Figure 6. Block diagram

4.2

FIFO

L3GD20H embeds 32 slots of 16-bit data FIFO for each of the three output channels: yaw,

pitch and roll. This allows consistent power saving for the system, since the host processor

does not need to continuously poll data from the sensor, but it can wakeup only when

needed and burst the significant data out from the FIFO. This buffer can work accordingly to

seven different modes: Bypass mode, FIFO-mode, Stream mode, Stream-to-FIFO mode,

Bypass-to-Stream, Dynamic-Stream, Bypass-to-FIFO. Each mode is selected by the FM2:0

bits in FIFO_CTRL register. Programmable FIFO threshold level, FIFO empty or FIFO

overrun events are available on FIFO_SRC register and can be set to generate dedicated

interrupts on DRDY/INT2 pin.

FIFO_SRC(EMPTY) is equal to '1' when no samples are available.

FIFO_SRC(FTH) goes to '1' if a new data arrives and FIFO_SRC(FSS4:0) is greater than or

equal

to FIFO Threshold configured to FTH4:0 into FIFO_CTRL (2Eh). FIFO_SRC(FTH)

goes to '0' if reading Yaw, Pitch and Roll data slot from FIFO and FIFO_SRC(FSS4:0) is

minor than or equal to FIFO_CTRL(FTH4:0).

ADC

LPF1

HPF

HPen

LPF2

Out_Sel

DataReg

Interrupt

generator

INT_Sel

I2C

SPI

INT1

SCR REG

CONF REG

FIFO

32x16x3

AM07230v1

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