L3GD20H datasheet(39/52 Pages) STMICROELECTRONICS

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L3GD20H

7.4

CTRL3 (22h)

7.5

CTRL4 (23h)

0100

0.05

0.1

0.2

0.5

0101

0.02

0.05

0.1

0.2

0.5

0110

0.01

0.02

0.05

0.1

0.2

0.5

0111

0.005

0.01

0.02

0.05

0.1

0.2

0.5

1000

0.002

0.005

0.01

0.02

0.05

0.1

0.2

1001

0.001

0.002

0.005

0.01

0.02

0.05

0.1

values in the table are indicative and they can vary proportionally with the specific ODR value

Table 26. High pass filter cut off frequency configuration [Hz](1) (continued)

HPCF3-0

ODR=12.5

ODR=25

ODR=50

ODR =100

ODR =200

ODR =400

ODR =800

Table 27. CTRL3 register

INT1_IG

INT1_Boot

H_Lactive

PP_OD

INT2_DRDY

INT2_FTH

INT2_ORun

INT2_Empty

Table 28. CTRL3 description

INT1_IG

Interrupt enable on INT1 pin. Default value 0. (0: disable; 1: enable)

INT1_Boot

Boot status available on INT1 pin. Default value 0. (0: disable; 1: enable)

H_Lactive

Interrupt active configuration on INT. Default value 0. (0: high; 1:low)

PP_OD

Push- Pull / Open drain. Default value: 0. (0: push-pull; 1: open drain)

INT2_DRDY

Date Ready on DRDY/INT2 pin. Default value 0. (0: disable; 1: enable)

INT2_FTH

FIFO Threshold interrupt on DRDY/INT2 pin. Default value: 0. (0: disable; 1: enable)

INT2_ORun

FIFO Overrun interrupt on DRDY/INT2 pin. Default value: 0. (0: disable; 1: enable)

INT2_Empty

FIFO Empty interrupt on DRDY/INT2 pin. Default value: 0. (0: disable; 1: enable)

Table 29. CTRL4 register

BDU

BLE

FS1

FS0

IMPen

ST2

ST1

SIM

Table 30. CTRL4 description

BDU

Block data update. Default value: 0

(0: continuos update; 1: output registers not updated until MSB and LSB read-

ing)

BLE

Big/little endian data selection. Default value 0.

(0: Data LSB @ lower address; 1: Data MSB @ lower address)

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