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L3GD20H 数据表(PDF) 48 Page - STMicroelectronics |
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L3GD20H 数据表(HTML) 48 Page - STMicroelectronics |
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48 / 52 page  Register description L3GD20H 48/52 DocID023469 Rev 2 7.24 LOW_ODR (39h) Table 62. LOW_ODR register -- -- DRDY_HL 0 (1) 1. These bits must be set to ‘0’ for proper working of the device. I2C_dis SW_RES 0 (1) Low_ODR Table 63. LOW_ODR description DRDY_HL DRDY/INT2 pin active level. Default value: 0 0 = DRDY active high 1 = DRDY active low I2C_dis 0 = both the I2C and SPI interfaces enabled (default) 1 = SPI only SW_RES Software reset. Default value: 0 0 = Normal Mode 1 = Reset Device (this bit is cleared by hardware after next flash boot) Low_ODR Low speed ODR. Default value: 0 Refer to Table 21 DR and BW configuration setting: for ODR and Bandwidth configuration on CTRL1 register 0 = Low Speed ODR disabled 1 = Low Speed ODR enabled |
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