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L3GD20H 数据表(PDF) 37 Page - STMicroelectronics |
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L3GD20H 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 52 page ![]() DocID023469 Rev 2 37/52 L3GD20H Register description Combination of PD, Zen, Yen, Xen are used to set device in different modes (power down / normal / sleep mode) according with the following table. Table 21. DR and BW configuration setting Low_ODR(1) 1. this bit is described in register LOW_ODR (39h register). DR <1:0> BW <1:0> ODR [Hz] Cut-Off [Hz](2) 2. values in the table are indicative and they can vary proportionally with the specific ODR value. 1 000012.5 n.a. 1 000112.5 n.a. 1 001012.5 n.a. 100 11 12.5 n.a. 1 010025 n.a. 1 010125 n.a. 1 011025 n.a. 101 11 25 n.a. 11X 00 50 16.6 11X 01 50 16.6 11X 10 50 16.6 11X 11 50 16.6 0 0000100 12.5 0 0001100 25 0 0010100 25 000 11 100 25 0 0100200 12.5 0 0101200 - 0 0110200 - 001 11 200 70 0 1000400 20 0 1001400 25 0 1010400 50 010 11 400 110 011 00 800 30 011 01 800 35 011 10 800 - 0 1111800 100 |
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