L3GD20H datasheet(40/52 Pages) STMICROELECTRONICS

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L3GD20H

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DocID023469 Rev 2

7.6

CTRL5 (24h)

FS1-FS0

Full scale selection. Default value: 00

(00: 245 dps; 01: 500 dps; 1x: 2000 dps)

IMPen

Level sensitive latched enable. Default value: 0

(0: level sensitive latched disabled; 1: level sensitive latched enabled)

ST2-ST1

Self-test enable. Default value: 00

00 = normal mode (default)

01 = self-test 0 (+)

10 = unused

11 = self-test 1(-)

SIM

SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 30. CTRL4 description (continued)

Table 31. CTRL5 register

BOOT

FIFO_EN

StopOnFTH

HPen

IG_Sel1

IG_Sel0

Out_Sel1

Out_Sel0

Table 32. CTRL5 description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content

(1)

)

Boot request is executed as soon as internal oscillator is turned-on. It is possibile to set bit while in Power-

down mode, in this case it will be served at the next normal mode or sleep mode.

FIFO_EN

FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO Enable)

StopOnFTH

Sensing chain FIFO stop values memorization at FIFO Threshold.

Default value: 0

0 = FIFO depth is not limited (32 digital words per axis)

1 = FIFO depth is limited to FIFO Threshold which is defined in

FIFO_CTRL (2Eh Register)

HPen

High Pass filter Enable. Default value: 0

(0: HPF disabled; 1: HPF enabled see

Figure 23.)

IG_Sel1-IG_Sel0

INT Generator selection configuration. Default value: 00

(See

Figure 23.)

Out_Sel1-Out_-

Sel0

Out selection configuration. Default value: 00

(See

Figure 23.)

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