L3GD20H datasheet(36/52 Pages) STMICROELECTRONICS

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L3GD20H

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The device contains a set of registers which are used to control its behavior and to retrieve

angular rate data. The registers address, made of 7 bits, is used to identify them and to write

the data through serial interface.

7.1

WHO_AM_I (0Fh)

Device identification register.

7.2

CTRL1 (20h)

DR<1:0> is used to set ODR selection. BW <1:0> is used to set bandwidth selection.

In the following table are reported all frequency resulting in combination of DR / BW bits.

Table 18. WHO_AM_I register

10101

Table 19. CTRL1 register(1)

Xen, Yen, Zen enable X, Yor Z register in level sensitive trigger mode. Once LVLen bit = 1, DEN level

replaces the LSB of X, Y or Z axes and all axis are available for reading.

DR1

DR0

BW1

BW0

Zen

Xen

Yen

Table 20. CTRL1 description

DR1-DR0

Output data rate selection. Refer to

Table 21

BW1-BW0

Bandwidth selection. Refer to

Table 21

Power mode. Default value: 0. Refer to

Table

0= Power Down

1= Normal Mode

(For Sleep Mode set {PD:Zen:Yen:Xen} to {1000})

Zen

Z axis enable. Default value: 1

(0: Z axis disabled; 1: Z axis enabled)

Yen

Y axis enable. Default value: 1

(0: Y axis disabled; 1: Y axis enabled)

Xen

X axis enable. Default value: 1

(0: X axis disabled; 1: X axis enabled)

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