A8603KESTR-R datasheet(38/42 Pages) ALLEGRO

38 / 42 page

Multiple-Output Regulator

for Automotive LCD Displays

A8603

A-1

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

I2C Interface Description

Appendix A

The A8603 provides an I2C-compliant serial interface that

exchanges commands and data between a system microcontroller

(master) and the A8603 (slave). Two bus lines, SCL and SDA,

provide access to the internal control registers. The clock input on

the SCL pin is generated by the master, while the SDA line func-

tions as either an input or an open drain output for the A8603,

depending on the direction of the data flow.

The I2C input thresholds depend on the VBIAS voltage of the

A8603. The threshold levels across the operating VBIAS range are

compatible with 3 V logic.

Timing Considerations

I2C communication is composed of several steps, in the following

sequence:

1. Start Condition. Defined by a negative edge on the SDA line,

while SCL is high (see figure A-1).

2. Address Cycle. 7 bits of address, plus 1 bit to indicate write (0)

or read (1), and an acknowledge bit (see figure A-2).

3. Data Cycles. Reading or writing 8 bits of data followed by an

acknowledge bit (see figure A-2).

4. Stop Condition. Defined by a positive edge on the SDA line,

while SCL is high (see figure A-1).

It is possible for the Start or Stop condition to occur at any time

during a data transfer. The A8603 always responds by resetting

the data transfer sequence. Except to indicate a Start or Stop con-

dition, SDA must be stable while the clock is high (figure A-2).

SDA can only be changed while SCL is low.

SDA

SCL

Start

Condition

Stop

Condition

SDA

SCL

(A) Start and Stop conditions

(B) Clock and data bit synchronization

Figure A-1. Bit transfer on the I2C bus

Figure A-2. Complete data transfer pulse train

Start

Condition

Stop

Condition

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

Slave Device Address

SDA

SCL

SDA

SCL

Acknowledge

Read/Write

Data (MSB byte)

Data (LSB byte)

D14 D13 D12 D11 D10 D9 D8

D6 D5 D4 D3 D2 D1 D0

D15

0/1

0/1 0/1 0/1 0/1 0/1 0/1 0/1

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

000

R/W

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