A8603KESTR-R datasheet(10/42 Pages) ALLEGRO

10 / 42 page

Multiple-Output Regulator for

Automotive LCD Displays

A8603

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

CHARACTERISTIC PERFORMANCE

VIN

(power supply)

(external enable)

BIAS

(IC internal supply)

FAULT

(pull-up to VIN)

<1 ms

I2C commands

Internal

Enable

AVDD

VCOM

VGL

VGH

Startup Timeout (10 to 99 ms)

tSU_TO

90%

t≥0

t1...t4 = startup delay (0 to 25.5 ms)

I2C Read/Write allowed at any time; however, user must not

make arbitrary changes in regulator target voltages; otherwise,

it may interfere with startup process or trip OVP/UVP.

Startup Timing Diagram

Sequence of events:

A:System controller brings EN = H to enable the A8603, provided that VIN is above UVLO level.

B:After A8603 performs a Power-On Reset (POR), it pulls down FAULT flag to signal that it is ready for I2C commands. (*)

C:System controller detected FAULT = L and sends in I2C command to clear POR status bit. This resets FAULT to H (unless there were other

faults detected).

D:After Programming the A8603 registers, system controller sets the regulator_internal_enable bit to 1 to turn on all output regulators.

(*) The delay time between EN = H and FAULT = L depends mainly on how fast the external BIAS capacitor can be charged up. For example, charging 1 µF at 5 mA from 0 to

2.8 V takes ~0.6 ms. Therefore, a 1 ms delay time is sufficient.

• Each regulator has a programmable Startup Delay timer. Each timer has a resolution of 0.1 ms and a maximum duration of 25.5 ms.

• VCOM cannot start before AVDD (because internally the VCOM regulator takes its power from AVDD output)

• VGH cannot start before VGL has reached 90% of its target voltage

• There is no dependency between {t1, t2} and {t3, t4}. That means VGL/VGH can start before or after AVDD/VCOM

• If any regulator output failed to reach 90% target after the Startup Timeout period (default 50 ms, starting from Internal Enable = H), the FAULT pin

will be pulled low and all outputs are shut down in an orderly manner. The IC will then retry after a Cool Down period.

Notes on Startup Timing Diagram

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