A8603KESTR-R datasheet(40/42 Pages) ALLEGRO

40 / 42 page

Multiple-Output Regulator

for Automotive LCD Displays

A8603

A-3

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

address, and finally the data. The address therefore consists of

two bytes, comprised of the A8603 chip address, with the write

enable bit, followed by the address of the individual register.

After each byte, the slave A8603 acknowledges by transmitting a

low to the master on the SDA line. After writing data to a register

the master must provide a Stop bit if writing is completed. Oth-

erwise, the master can continue sending data to the device and it

will automatically increase the register value by one for addi-

tional data byte. This allows faster data entry but restricts the data

entry to sequential registers.

I2C Command Read from the A8603

The master can read back the register values of the A8603. The

Read command is given in the R/¯

¯ bit of the address byte. To do

so, the master transmits data bits to the SDA input of the A8603,

synchronized with the clocking signal the master transmits

simultaneously on the SCL input. The pulse train is shown in fig-

ure A-4. A complete transmission begins with the master pulling

SDA low (Start bit), and completes with the master releasing the

SDA pin (Stop bit). Between these points, the master transmits

a pattern of chip address with the Read command (R/¯

¯ = 1) and

then the address of the register to be read. Again, the address

consists of two bytes, comprising the address of the A8603 (chip

address) with the read enable bit, followed by the address of

the individual register. The bus master then executes a Master

Restart, reissues the slave address, then the A8603 exports the

data byte for that register, synchronized with the clock pulse sup-

plied by the master. The master must provide the clock pulses, as

the A8603 slave does not have the capability to generate them.

If the master does not send an non-acknowledge bit (AK = 1)

after receiving the data, the A8603 will continue sending data

from the sequential registers after the addressed one, as shown in

figure A-3. After the master provides an non-acknowledge bit, the

A8603 will stop sending the data. After that, if additional register

reads are required, the process must start over again.

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