Multiple-Output Regulator for

Automotive LCD Displays

A8603

4

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Terminal List Table

Number

Name

Function

1

VIN

Input supply voltage (3 to 10 V) for the IC

2

FAULT

Open-drain output, pulls low in case of error condition

3

EN

4

VCOM

Output from internal low-dropout (LDO) regulator (item 2 in Functional Block Diagram) powered by AVDD

5

GNDVCOM Ground reference for VCOM; connect to ground plane

6

NC

No Connect (reserved for Test Mode); connect to GND in actual PCB

7

SCL

8

SDA

9

ADDR

10

FSET

Input for synchronizing boost and charge pump signals switching frequency to external clock signal; alternatively, it can be

connected to an external resistor to set the switching frequency

11

BIAS

Output from internal 2.8 V bias regulator; connect to GND via 1 μF ceramic capacitor for decoupling

12

COMP

13

AVDD

14

AGND

Analog GND reference for signals; connect to ground plane

15

VGL

Inverted charge pump output (item 3 in Functional Block Diagram)

16

CP22

Capacitor terminals for inverted charge pump (item 3 in Functional Block Diagram)

17

CP21

18

VGH

2× charge pump output (item 4 in Functional Block Diagram)

19

VGH3

3× charge pump output (item 4 in Functional Block Diagram)

20

CP11

Capacitor terminals for charge pump (item 4 in Functional Block Diagram)

21

CP12

22

VOUT

Connect to boost output for internal LDO and charge pump regulators

23

PGND

Power ground for internal boost switch; connect this pin to ground terminal of output ceramic capacitor(s)

24

SW

Internal boost converter switch node

–

PAD

Package ES, 24-Pin QFN Pinouts

1

EN

2

VCOM

3

GNDVCOM

4

5

6

NC

AVDD

AGND

13

VGL

14

CP22

15

CP21

16

VGH

17

18

VIN

FAULT

PAD

PINOUT DIAGRAMS AND TERMINAL LIST TABLE