A8603KESTR-R datasheet(12/42 Pages) ALLEGRO

12 / 42 page

Multiple-Output Regulator for

Automotive LCD Displays

A8603

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

FUNCTIONAL DESCRIPTION

The A8603 is a flexible multivoltage regulator designed for LCD

panel bias applications. It utilizes a high-efficiency boost con-

verter, together with space-saving low-dropout (LDO) regulator

and charge pump circuits to provide four independently adjust-

able voltage outputs:

• AVDD: Typically between 5 and 15 V. Nominal output current

100 mA. This output is from a LDO powered by VOUT.

• VCOM: Typically between 3 and 7.5 V at 20 mA. The power

supply of this regulator is internally connected to AVDD.

Therefore AVDD must be at least 1.5 V higher than the upper

limit of VCOM.

• VGL: Typically between –12 and –4 V at 4 mA. This voltage

is generated by an inverted charge pump, which is powered by

VOUT.

• VGH: Typically between 10 and 24 V at 4 mA. This voltage is

generated by a 2× charge pump, which is powered by VOUT.

If necessary, an external 3× charge pump can generate a higher

VGH between 20 and 30 V at 4 mA.

Program Diagnostics

A8603 features the I2C (Inter-Integrated Circuit, alternatively

spelled as I2C) serial interface and programmable memory array.

The I2C serial interface allows external microcontroller or some

type of master device to communicate with A8603 as its slave

Micro

Controller

SCL

SDA

Driver

ADDR

2 Bit

Decoder

clock

data_in

data_out

addr<1:0>

I2C

Interface

Read/Write

A8603

Figure 1: I2C Serial Interface and Programmable

Memory Array

device. Two bus lines, SCL and SDA, provide access to the inter-

nal control registers. The clock input on the SCL pin is generated

by the master, while the SDA line functions as either an input or

an open-drain output for the A8603, depending on the direction

of the data flow.

In case there are two or more slave devices in an I2C network,

each device must present a unique physical address for the master

to select. To avoid conflict, the A8603 uses a 4-level ADDR pin

to set its physical address. Depending on the voltage level at

ADDR, the physical address is set as ‘101,00xx’, where

xx = {00 | 01 | 10 | 11}. This is illustrated by the figure below.

I2C

Interface

SDA

SCL

ADDR

BIAS

(2.8 V)

Figure 2: Select I2C Address by Using Resistor Divider

at ADDR Pin

Table 1: I2C Address Selection Using Resistor Divider

R1 (k)

R2 (k)

VADDR (V)

I2C Address

open

101,0000

27.4

0.75

101,0001

6.98

1.65

101,0010

open

2.8

101,0011

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