Multiple-Output Regulator for

Automotive LCD Displays

A8603

16

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Latched Status Registers

Registers 0x17 to 0x1B hold the status bits after a fault has

occurred. Each bit is read-only and can be only cleared by writing

a ‘1’ to it. In case of a fault shutdown, the user can read those

registers to determine the cause of the shutdown, and then clear

them by writing ‘0xFF’ to each register.

Table 9: Register 0x17 – Latched Output Over- and Undervoltage Protection Fault

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

VGH > 120%

VGL > 120%

VCOM > 120%

AVDD > 120%

VGH < 80%

VGL < 80%

VCOM < 80%

AVDD < 80%

Each bit is set to ‘1’ when its corresponding regulator has tripped OVP/UVP fault. Note that those bits can only be set after all regulators have finished startup stage and the IC

is in normal operation mode.

Table 10: Register 0x18 – Latched Output Overcurrent Protection Fault

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Reserved

-

-

-

VGH ILimit

VGL ILimit

VCOM ILimit

AVDD ILimit

Each bit is set to ‘1’ when its corresponding regulator is operating at current limit during normal operation.

Table 11: Register 0x19 – Latched Fault Status

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

FAULT

MaxRetry

Watchdog

SW ILimit2

SW OVP

Rail Fault

FSET fault

TSD

See Register 0x16 for explanation of each bit.

Table 12: Register 0x1A – Latched Non-Fault Status

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Current Retry Counter (Read-Only)

SW ILimit1

Slow Shutdown

Hard Reset

Power-On Reset

Bit[4..7] = Current Retry Counter (0 to 15)

Bit3 = 1 if boost switch cycle-by-cycle current limit has be reached. This is not a fault condition and IC does not shutdown.

Bit2 = 1 if during shutdown, any regulator failed to decay below 10% (AVDD/VCOM) or 30% (VGL/VGH) before watchdog timer expires. This is not a fault since the IC still

shuts down afterward.

Bit1 = 1 if the IC has finished a hardware-initiated shutdown (by EN = L briefly) and all registers are restored to default values.

Bit0 = 1 if the IC has finished a power-on reset and all registers are initialized to their default values.

Note that after a Power-On Reset (or a Hard Reset), the output regulator cannot be enabled until bit0 (or bit1) is cleared. This can be done by writing a ‘0x03’ to Register0x1A.

Table 13: Register 0x1B – Latched Over- and Undervoltage Status During Startup

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

VGH > 120%

VGL > 120%

VCOM > 120%

AVDD > 120%

VGH < 80%

VGL < 80%

VCOM < 80%

AVDD < 80%

This is similar to Register 0x17, except it only records OVP/UVP during startup phase. Suppose, under certain unlikely situations, a regulator output rises above 120% or

drops below 80% after it reached 90% but before the IC enters normal operation mode, then it will be recorded.