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A8603KESTR-R 数据表(PDF) 39 Page - Allegro MicroSystems

部件名 A8603KESTR-R
功能描述  Multiple-Output Regulator for Automotive LCD Displays
PDF  42 Pages
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制造商  ALLEGRO [Allegro MicroSystems]
网页  http://www.allegromicro.com
标志 ALLEGRO - Allegro MicroSystems

A8603KESTR-R 数据表(HTML) 39 Page - Allegro MicroSystems

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Multiple-Output Regulator
for Automotive LCD Displays
A8603
A-2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The state of the Read/Write bit (R/¯
W
¯ ) is set low to indicate a
Write cycle and set high to indicate a Read cycle.
The master monitors for an acknowledge bit to determine if the
slave device is responding to the address byte sent to the A8603.
When the A8603 decodes the 7-bit address field as a valid
address, it acknowledges by pulling SDA low during the ninth
clock cycle.
During a data write from the master, the A8603 pulls SDA low
during the clock cycle that follows each data byte, in order to
indicate that the data has been successfully received.
After sending either an address byte or a data byte, the master
device must release the SDA line before the ninth clock cycle, in
order to allow the handshaking to occur.
I2C Command Write to the A8603
The master controls the A8603 by programming it as a slave.
To do so, the master transmits data bits to the SDA input of the
A8603, synchronized with the clocking signal the master trans-
mits simultaneously on the SCL input (figure A-3).
A complete transmission begins with the master pulling SDA low
(Start bit), and completes with the master releasing the SDA line
(Stop bit). Between these points, the master transmits a pattern of
address bits with a Write command bit (R/¯
W
¯ ), then the register
Figure A-3. Writing to single and to multiple registers
Start
Condition
Stop
Condition
Stop
Condition
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A0
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
AK
AK
Register Address
Slave Device Address
SDA
SCL
AK
Write
1
2
3
4
5
6
7
8
9
Data
D6 D5
D4 D3 D2 D1 D0
D7
0
0/1 0/1 0/1 0/1 0/1 0/1 0/1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
000
R/W
Start
Condition
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A0
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
AK
AK
Register N Address
Slave Device Address
Write to a single register
Write to multiple registers
SDA
SCL
AK
Slave
Acknowledge
Slave
Acknowledge
Slave
Acknowledge
Slave
Acknowledge
Slave
Acknowledge
Slave
Acknowledge
Slave
Acknowledge
Slave
Acknowledge
Write
1
2
3
4
5
6
7
8
9
Register N Data
Register N+1 Data
[Wraps to Register N+1]
Register N+n Data
0
0/1 0/1 0/1 0/1 0/1 0/1 0/1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
000
R/W
AK
1
2
3
4
5
6
7
8
9
[Wraps to Register N+n]
0
AK
1
2
3
4
5
6
7
8
9
0
D6 D5
D4 D3 D2 D1 D0
D7
D6 D5
D4 D3 D2 D1 D0
D7
D6 D5
D4 D3 D2 D1 D0
D7
SDA
SCL
SDA
SCL



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