Multiple-Output Regulator for

Automotive LCD Displays

A8603

11

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

AB

CD

VIN

(power supply)

EN

(external enable)

BIAS

(IC internal supply)

FAULT

(pull-up to VIN)

Internal

Enable

AVDD

VCOM

VGL

VGH

t5

t6

t7

t≥0

t8

30%

Shutdown Timeout (50 ms)

Shutdown Timing Diagram

Sequence of events:

defaults at the end of a Hardware Shutdown. This does not apply to a Software Shutdown when user programs INT_EN = L.

• Each regulator has a programmable Shutdown Delay timer. Each timer has a resolution of 0.1 ms and a maximum duration of 25.5 ms.

• AVDD can only be turned off after VCOM is turned off (t5 = 0 is allowed)

• VGL can only be turned off after VGH drops below 30%, even through t7 = 0 is allowed.

• There is no dependency between {t5, t6} and {t7, t8}

• Once a shutdown is in progress, both external Enable and Internal EN are ignored until shutdown is completed.

• All output discharge times are based on external capacitance and internal pull-down resistance (250 Ω for AVDD and VCOM, 500 Ω for VGH and

VGL). The external DC load is assumed to be negligible.

• If any of the regulator output does not decay to below 10% (30% for VGL and VGH) of target voltage after 50 ms time-out period, starting from

beginning of shutdown, it is ignored and then the IC is allowed to power down.

Notes on Shutdown Timing Diagram