COP8-REF-AM datasheet(19/83 Pages) NSC

19 / 83 page

10.0 Functional Description

(Continued)

;options

.endsect

Example: The following sets a value in the Option Register

for a COP8AME9. The Option Register bit values shown

select options: Security disabled, WATCHDOG enabled

HALT mode enabled and execution will commence from

Flash Memory.

.chip

8AME

.sect

option, conf

.db

0x01

;wd, halt, flex

.endsect

...

.end

start

Note: All programmers certified for programming this family

of parts will support programming of the Option Register.

Please contact National or your device programmer supplier

for more information.

10.6 SECURITY

The device has a security feature which, when enabled,

prevents external reading of the Flash program memory. The

security bit in the Option Register determines, whether se-

curity is enabled or disabled. If the security feature is dis-

abled, the contents of the internal Flash Memory may be

read

external

programmers

the

built

MICROWIRE/PLUS serial interface ISP. Security must be

enforced by the user when the contents of the Flash

Memory are accessed via the user ISP or Virtual EE-

PROM capability.

If the security feature is enabled, then any attempt to exter-

nally read the contents of the Flash Memory will result in the

value FF (hex) being read from all program locations (except

the Option Register). In addition, with the security feature

enabled, the write operation to the Flash program memory

and Option Register is inhibited. Page Erases are also inhib-

ited when the security feature is enabled. The Option Reg-

ister is readable regardless of the state of the security bit by

accessing location FFFF (hex). Mass Erase Operations are

possible regardless of the state of the security bit.

The security bit can be erased only by a Mass Erase of the

entire contents of the Flash unless Flash operation is under

the control of User ISP functions.

Note: The actual memory address of the Option Register is

1FFF (hex), however the MICROWIRE/PLUS ISP routines

require the address FFFF (hex) to be used to read the

Option Register when the Flash Memory is secured.

The entire Option Register must be programmed at one time

and cannot be rewritten without first erasing the entire last

page of Flash Memory.

10.7 RESET

The device is initialized when the RESET pin is pulled low or

the On-chip Brownout Reset is activated.

The following occurs upon initialization:

Port B: TRI-STATE (High Impedance Input)

Port G: TRI-STATE (High Impedance Input). Exceptions: If

Watchdog is enabled, then G1 is Watchdog output. G0 and

G2 have their weak pull-up enabled during RESET.

Port L: TRI-STATE (High Impedance Input)

PC: CLEARED to 0000

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

T2CNTRL: CLEARED

T3CNTRL: CLEARED

HSTCR: CLEARED

ITMR: Cleared except Bit 6 (HSON) = 1

Accumulator, Timer 1, Timer 2 and Timer 3:

RANDOM after RESET

WKEN, WKEDG: CLEARED

WKPND: RANDOM

SP (Stack Pointer):

Initialized to RAM address 06F Hex

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

S Register: CLEARED

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

USART:

PSR, ENU, ENUR, ENUI: Cleared, except the TBMT bit

which is set to one.

ANALOG TO DIGITAL CONVERTER:

ENAD: CLEARED

ADRSTH: RANDOM

ADRSTL: RANDOM

Op Amp:

AMPTRMN, AMPTRMP: Cleared, except bit6=1

ADGAIN: CLEARED

ISP CONTROL:

ISPADLO: CLEARED

ISPADHI: CLEARED

PGMTIM: PRESET TO VALUE FOR 10 MHz CKI

20006311

FIGURE 7. Reset Logic

COP8-REF-AM 数据表(PDF) 19 Page - National Semiconductor (TI)

COP8-REF-AM 数据表(HTML) 19 Page - National Semiconductor (TI)

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