COP8-REF-AM datasheet(48/83 Pages) NSC

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14.0 USART (Continued)

Using the above equationNxP can be calculated first.

NxP =(5x10

6 x 2)/(16 x 19200) = 32.552

Now 32.552 is divided by each Prescaler Factor (Table 20)to

obtain a value closest to an integer. This factor happens to

be 6.5 (P = 6.5).

N = 32.552/6.5 = 5.008 (N = 5)

The programmed value (from Table 19) should be 4 (N - 1).

Using the above values calculated for N and P:

BR=(5x10

6 x 2)/(16x5x 6.5) = 19230.769

error = (19230.769 - 19200) x 100/19200 = 0.16%

14.8 EFFECT OF HALT/IDLE

The USART logic is reinitialized when either the HALT or

IDLE modes are entered. This reinitialization sets the TBMT

flag and resets all read only bits in the USART control and

status registers. Read/Write bits remain unchanged. The

Transmit Buffer (TBUF) is not affected, but the Transmit Shift

RBUF and RSFT are not affected.

The device will exit from the HALT/IDLE modes when the

Start bit of a character is detected at the RDX (L3) pin. This

feature is obtained by using the Multi-Input Wake-up scheme

provided on the device.

Before entering the HALT or IDLE modes the user program

must select the Wake-up source to be on the RDX pin. This

selection is done by setting bit 3 of WKEN (Wake-up Enable)

high to low transition. This is done via the WKEDG register

(Bit 3 is one).

If the device is halted and crystal oscillator is used, the

Wake-up signal will not start the chip running immediately

because of the finite start up time requirement of the crystal

oscillator. The IDLE timer (T0) generates a fixed (256 t

delay to ensure that the oscillator has indeed stabilized

before allowing the device to execute code. The user has to

consider this delay when data transfer is expected immedi-

ately after exiting the HALT mode.

14.9 DIAGNOSTIC

Bits CHL0 and CHL1 in the ENU register provide a loopback

feature for diagnostic testing of the USART. When both bits

are set to one, the following occurs: The receiver input pin

(RDX) is internally connected to the transmitter output pin

(TDX); the output of the Transmitter Shift Register is “looped

back” into the Receive Shift Register input. In this mode,

data that is transmitted is immediately received. This feature

allows the processor to verify the transmit and receive data

paths of the USART.

Note that the framing format for this mode is the nine bit

format; one Start bit, nine data bits, and one or two Stop bits.

Parity is not generated or verified in this mode.

14.10 ATTENTION MODE

The USART Receiver section supports an alternate mode of

operation, referred to as ATTENTION Mode. This mode of

operation is selected by the ATTN bit in the ENUR register.

The data format for transmission must also be selected as

having nine Data bits and either one or two Stop bits.

The ATTENTION mode of operation is intended for use in

networking the device with other processors. Typically in

such environments the messages consists of device ad-

dresses, indicating which of several destinations should re-

ceive them, and the actual data. This Mode supports a

scheme in which addresses are flagged by having the ninth

bit of the data field set to a 1. If the ninth bit is reset to a zero

the byte is a Data byte.

While in ATTENTION mode, the USART monitors the com-

munication flow, but ignores all characters until an address

character is received. Upon receiving an address character,

the USART signals that the character is ready by setting the

RBFL flag, which in turn interrupts the processor if USART

Receiver interrupts are enabled. The ATTN bit is also cleared

automatically at this point, so that data characters as well as

address characters are recognized. Software examines the

contents of the RBUF and responds by deciding either to

accept the subsequent data stream (by leaving the ATTN bit

reset) or to wait until the next address character is seen (by

setting the ATTN bit again).

Operation of the USART Transmitter is not affected by se-

lection of this Mode. The value of the ninth bit to be trans-

mitted is programmed by setting XBIT9 appropriately. The

value of the ninth bit received is obtained by reading RBIT9.

Since this bit is located in ENUR register where the error

flags reside, a bit operation on it will reset the error flags.

14.11 BREAK GENERATION

To generate a line break, the user software should set the

BRK bit in the ENUI register. This will force the TDX pin to 0

and hold it there until the BRK bit is reset.

20006328

FIGURE 24. USART BAUD Clock Divisor Registers

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