COP8-REF-AM datasheet(32/83 Pages) NSC

32 / 83 page

12.0 Timers (Continued)

If either T2 or T3 is used in High Speed PWM mode and an

SBIT or RBIT instruction operates on any other bit of the

PORT L Data Register, the PWM output may appear to miss

a toggle and thus be inverted. If the timer causes the PWM

output to toggle in the middle of an SBIT or RBIT operation

on the PORTLD Register, the PWM output may be set back

to its state before the output toggle by the operation of the

SBIT/RBIT. This can have the effect of generating a short-

ened pulse (less than one instruction cycle in width) on the

PWM output and inverting the PWM duty cycle.

If the PWM Timer is used in low speed mode or if the PWM

output toggle is synchronous with the end of the instruction

cycle, this problem is not seen. The following figure illus-

trates the PWM output when the failure is seen.

The user should be aware of the state of Timers T2 and T3

before any SBIT or RBIT instructions are executed which

operate on the PORTLD register. If the PWM output is close

to toggling, the user should delay the SBIT or RBIT instruc-

tion.

The following program sequence works to delay the opera-

tion. The user may wish to experiment with other sequences

to see which best fits the application and to make sure that

the time between the completion of the tests and the modi-

fication of PORTLD is not too long. The sequence can easily

be modified to work with Timer T3.

LD B,#TMR2HI ;POINT B TO THE TIMER

LD A,[B-] ;GET THE VALUE IN THE TIMER

IFGT A,#0 ;IF NON ZERO

JP GOOD ;WE HAVE TIME

WAIT: IFBIT 6,[B] ;TEST BIT 6 OF THE TIMER

JP GOOD ;TIME TO GET IT DONE SAFELY

JP WAIT ;WAIT A WHILE

GOOD: SBIT 2,PORTLD ;GO AHEAD AND SET THE

BIT

⇒

The above program uses specific bits of the port for expla-

nation purposes only.

The above program uses the SBIT instruction by way of

example. The RBIT instruction will have the same effect.

The above sequence will not work properly for PWM times

shorter than 64 CPU Clock cycles.

The choice of TMR2LO bit 6 works, but may introduce delay

at the wrong time in some applications, particularly if bit 7 is

a one. The above example shows the workaround if only one

timer (T2 or T3) is used in high speed PWM mode. If both

Timers T2 and T3 are used in high speed PWM mode, the

program becomes significantly more complicated, since the

execution of the SBIT or RBIT instruction must be delayed

until the PWM output of neither T2 nor T3 is likely to change

during the execution of the instruction.

12.2.3 Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin after

synchronization to the appropriate internal clock (t

MCLK). The Tx timer control bits, TxC3, TxC2 and TxC1

allow the timer to be clocked either on a positive or negative

edge from the TxA pin. Underflows from the timer are latched

into the TxPNDA pending flag. Setting the TxENA control flag

will cause an interrupt when the timer underflows.

In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB

control flag is set. The occurrence of a positive edge on the

TxB input pin is latched into the TxPNDB flag.

Figure 16 shows a block diagram of the timer in External

Event Counter mode.

Note: The PWM output is not available in this mode since the

TxA pin is being used as the counter input clock.

12.2.4 Mode 3. Input Capture Mode

The device can precisely measure external frequencies or

time external events by placing the timer block, Tx, in the

input capture mode. In this mode, the reload registers serve

as independent capture registers, capturing the contents of

the timer when an external event occurs (transition on the

timer input pin). The capture registers can be read while

maintaining count, a feature that lets the user measure

elapsed time and time between events. By saving the timer

value when the external event occurs, the time of the exter-

nal event is recorded. Most microcontrollers have a latency

time because they cannot determine the timer value when

20006319

FIGURE 15. Timer in PWM Mode

20006320

FIGURE 16. Timer in External Event Counter Mode

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