COP8-REF-AM datasheet(59/83 Pages) NSC

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18.0 Interrupts (Continued)

The default VIS interrupt vector can be useful for applica-

tions in which time critical interrupts can occur during the

servicing of another interrupt. Rather than restoring the pro-

gram context (A, B, X, etc.) and executing the RETI instruc-

tion, an interrupt service routine can be terminated by return-

ing to the VIS instruction. In this case, interrupts will be

serviced in turn until no further interrupts are pending and

the default VIS routine is started. After testing the GIE bit to

ensure that execution is not erroneous, the routine should

restore the program context and execute the RETI to return

to the interrupted program.

This technique can save up to fifty instruction cycles (t

C), or

more, (25 µs at 10 MHz oscillator) of latency for pending

interrupts with a penalty of fewer than ten instruction cycles

if no further interrupts are pending.

To ensure reliable operation, the user should always use the

VIS instruction to determine the source of an interrupt. Al-

though it is possible to poll the pending bits to detect the

source of an interrupt, this practice is not recommended. The

use of polling allows the standard arbitration ranking to be

altered, but the reliability of the interrupt system is compro-

mised. The polling routine must individually test the enable

and pending bits of each maskable interrupt. If a Software

Trap interrupt should occur, it will be serviced last, even

though it should have the highest priority. Under certain

conditions, a Software Trap could be triggered but not ser-

viced, resulting in an inadvertent “locking out” of all

maskable interrupts by the Software Trap pending flag.

Problems such as this can be avoided by using VIS

instruction.

TABLE 33. Interrupt Vector Table

Arbitration Ranking

Source Description

Vector Address (Note 16)

(Hi-Low Byte)

(1) Highest

Software

INTR Instruction

0yFE–0yFF

(2)

Reserved for NMI

0yFC–0yFD

(3)

External

0yFA–0yFB

(4)

Timer T0

Underflow

0yF8–0yF9

(5)

Timer T1

T1A/Underflow

0yF6–0yF7

(6)

Timer T1

T1B

0yF4–0yF5

(7)

MICROWIRE/PLUS

BUSY Low

0yF2–0yF3

(8)

Reserved

0yF0–0yF1

(9)

USART

Receive

0yEE–0yEF

(10)

USART

Transmit

0yEC–0yED

(11)

Timer T2

T2A/Underflow

0yEA–0yEB

(12)

Timer T2

T2B

0yE8–0yE9

(13)

Timer T3

T2A/Underflow

0yE6–0yE7

(14)

Timer T3

T3B

0yE4–0yE5

(15)

Port L/Wakeup

Port L Edge

0yE2–0yE3

(16) Lowest

Default VIS

Reserved

0yE0–0yE1

Note 16: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last

address of a block. In this case, the table must be in the next block.

18.3.1 VIS Execution

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc....) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FA is generated and so forth. If no active interrupt

is pending, than E0 is generated. This number replaces the

lower byte of the PC. The upper byte of the PC remains

unchanged. The new PC is therefore pointing to the vector of

the active interrupt with the highest arbitration ranking. This

vector is read from program memory and placed into the PC

which is now pointed to the 1st instruction of the service

routine of the active interrupt with the highest arbitration

ranking.

Figure 32 illustrates the different steps performed by the VIS

instruction. Figure 33 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

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