COP8-REF-AM datasheet(31/83 Pages) NSC

31 / 83 page

12.0 Timers (Continued)

12.1.1 ITMR Register

LSON

HSON

DCEN

CCK

SEL

RSVD ITSEL2 ITSEL1 ITSEL0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bits 7–4: Described

Section

13.0

Power

Saving

Features.

Note: Documentation for previous COP8 devices, which in-

cluded the Programmable Idle Timer, recommended the user

write zero to the high order bits of the ITMR Register. If

existing programs are updated to use this device, writing

zero to these bits will cause the device to reset (see Section

13.0 Power Saving Features).

RSVD: This bit is reserved and must be set to 0.

ITSEL2:0: Selects the Idle Timer period as described in

Table 14, Idle Timer Window Length.

Any time the IDLE Timer period is changed there is the

possibility of generating a spurious IDLE Timer interrupt by

setting the T0PND bit. The user is advised to disable IDLE

Timer interrupts prior to changing the value of the ITSEL bits

of the ITMR Register and then clear the T0PND bit before

attempting to synchronize operation to the IDLE Timer.

12.2 TIMER T1, TIMER T2, AND TIMER T3

The device has a set of three powerful timer/counter blocks,

T1, T2, and T3. Since T1, T2 and T3 are identical, except for

the high speed operation of T2 and T3, all comments are

equally applicable to any of the three timer blocks which will

be referred to as Tx. Differences between the timers will be

specifically noted.

The core 16-bit timer is designated T1, this section uses Tx

to refer to timer T1 and all additional timers that operate in

exactly the same manner as timer T1, with the exception of

the high speed capability described later.

Each timer block consists of a 16-bit timer, Tx, and two

supporting 16-bit autoreload/capture registers, RxA and

RxB. Each timer block has two pins associated with it, TxA

and TxB. The pin TxA supports I/O required by the timer

block, while the pin TxB is an input to the timer block. The

timer block has three operating modes: Processor Indepen-

dent PWM mode, External Event Counter mode, and Input

Capture mode.

The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

12.2.1 Timer Operating Speeds

Each of the Tx timers, except T1, have the ability to operate

at either the instruction cycle frequency (low speed) or the

internal clock frequency (MCLK). For 10 MHz CKI, the in-

struction cycle frequency is 2 MHz and the internal clock

frequency is 20 MHz. This feature is controlled by the High

Speed Timer Control Register, HSTCR. Its format is shown

below. To place a timer, Tx, in high speed mode, set the

appropriate TxHS bit to 1. For low speed operation, clear the

appropriate TxHS bit to 0. This register is cleared to 00 on

Reset.

The T2IDLE bit is used to allow T2 operation while the

device is in Idle mode. See Section 12.4 TIMER T2 OPERA-

TION IN IDLE MODE for further information.

HSTCR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit

T2IDLE

00000

T3HS

T2HS

12.2.2 Mode 1. Processor Independent PWM Mode

One of the timer’s operating modes is the Processor Inde-

pendent PWM mode. In this mode, the timers generate a

“Processor Independent” PWM signal because once the

timer is set up, no more action is required from the CPU

which translates to lower software overhead and greater

throughput. The user software services the timer block only

when the PWM parameters require updating. This capability

is provided by the fact that the timer has two separate 16-bit

reload registers. One of the reload registers contains the

“ON” time while the other holds the “OFF” time. By contrast,

a microcontroller that has only a single reload register re-

quires an additional software to update the reload value

(alternate between the on-time/off-time).

The timer can generate the PWM output with the width and

duty cycle controlled by the values stored in the reload

registers. The reload registers control the countdown values

and the reload values are automatically written into the timer

when it counts down through 0, generating interrupt on each

reload. Under software control and with minimal overhead,

the PWM outputs are useful in controlling motors, triacs, the

intensity of displays, and in providing inputs for data acqui-

sition and sine wave generators.

In this mode, the timer Tx counts down at a fixed rate of t

(T2 and T3 may be selected to operate from MCLK). Upon

every underflow the timer is alternately reloaded with the

contents of supporting registers, RxA and RxB. The very first

underflow of the timer causes the timer to reload from the

reloaded from the registers alternately beginning with the

Figure 15 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the TxA output

pin. The underflows can also be programmed to generate

interrupts.

Underflows from the timer are alternately latched into two

pending flags, TxPNDA and TxPNDB. The user must reset

these pending flags under software control. Two control

enable flags, TxENA and TxENB, allow the interrupts from

the timer underflow to be enabled or disabled. Setting the

timer enable flag TxENA will cause an interrupt when a timer

underflow causes the RxA register to be reloaded into the

timer. Setting the timer enable flag TxENB will cause an

interrupt when a timer underflow causes the RxB register to

be reloaded into the timer. Resetting the timer enable flags

will disable the associated interrupts.

Either or both of the timer underflow interrupts may be

enabled. This gives the user the flexibility of interrupting

once per PWM period on either the rising or falling edge of

the PWM output. Alternatively, the user may choose to inter-

rupt on both edges of the PWM output.

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