COP8-REF-AM datasheet(29/83 Pages) NSC

29 / 83 page

11.0 In-System Programming (Continued)

TABLE 12. Register and Bit Name Definitions

Name

Purpose

RAM

Location

ISPADHI

High byte of Flash Memory Address

0xA9

ISPADLO

Low byte of Flash Memory Address

0xA8

ISPWR

The user must store the byte to be written into this register before jumping into the

write byte routine.

0xAB

ISPRD

Data will be returned to this register after the read byte routine execution.

0xAA

ISPKEY

The ISPKEY Register is required to validate the JSRB instruction and must be loaded

within 6 instruction cycles before the JSRB.

0xE2

BYTECOUNTLO

Holds the count of the number of bytes to be read or written in block operations.

0xF1

PGMTIM

Write Timing Register. This register must be loaded, by the user, with the proper value

before execution of any USER ISP Write or Erase operation. Refer to Table 8 for the

correct value.

0xE1

Confirmation Code

The user must place this code in the accumulator before execution of a Flash Memory

Mass Erase command.

KEY

Must be transferred to the ISPKEY register before execution of a JSRB instruction.

0x98

11.9 RESTRICTIONS ON SOFTWARE WHEN CALLING

ISP ROUTINES IN BOOT ROM

The hardware will disable interrupts from occurring. The

hardware will leave the GIE bit in its current state, and if

set, the hardware interrupts will occur when execution is

returned to Flash Memory. Subsequent interrupts, dur-

ing ISP operation, from the same interrupt source will be

lost. Interrupt may occur between setting the KEY

and executing the JSRB instruction. In this case, the

KEY will expire before the JSRB is executed. It is,

therefore, recommended that the software globally

disable interrupts before setting the Key.

The security feature in the MICROWIRE/PLUS ISP is

guaranteed by software and not hardware. When ex-

ecuting the MICROWIRE/PLUS ISP routine, the security

bit is checked prior to performing all instructions. Only

the mass erase command, write PGMTIM register, and

reading the Option register is permitted within the

MICROWIRE/PLUS ISP routine. When the user is per-

forming his own ISP, all commands are permitted. The

entry points from the user’s ISP code do not check for

security. It is the burden of the user to guarantee his own

security. See the Security bit description in Section 10.5

OPTION REGISTER for more details on security.

When using any of the ISP functions in Boot ROM, the

ISP routines will service the WATCHDOG within the

selected upper window. Upon return to flash memory,

the WATCHDOG is serviced, the lower window is en-

abled, and the user can service the WATCHDOG any-

time following exit from Boot ROM, but must service it

within the selected upper window to avoid a WATCH-

DOG error.

Block Writes can start anywhere in the page of Flash

memory, but cannot cross half page or full page bound-

aries.

The user must ensure that a page erase or a mass

erase is executed between two consecutive writes to

the same location in Flash memory. Two writes to

the same location without an intervening erase will

produce unpredicatable results including possible

disturbance of unassociated locations.

11.10 FLASH MEMORY DURABILITY CONSIDERATIONS

The endurance of the Flash Memory (number of possible

Erase/Write cycles) is a function of the erase time and the

lowest temperature at which the erasure occurs. If the device

is to be used at low temperature, additional erase operations

can be used to extend the erase time. The user can deter-

mine how many times to erase a page based on what

endurance is desired for the application (e.g. four page

erase cycles, each time a page erase is done, may be

required to achieve the typical 100k Erase/Write cycles in an

application which may be operating down to 0˚C). Also, the

customer can verify that the entire page is erased, with

software, and request additional erase operations if desired.

TABLE 13. Typical Flash Memory Endurance

Low End of Operating Temp Range

Erase

Time

−40˚C

−20˚C

0˚C

25˚C

>25˚C

1 ms

60k

100k

2 ms

60k

100k

3 ms

60k

100k

4 ms

60k

100k

5 ms

70k

100k

6 ms

80k

100k

7 ms

90k

100k

8 ms

100k

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