COP8-REF-AM datasheet(8/83 Pages) NSC

8 / 83 page

6.0 Architectural Overview

6.1 EMI REDUCTION

The COP8AME9 device incorporates circuitry that guards

against electromagnetic interference - an increasing problem

in today’s microcontroller board designs. National’s patented

EMI reduction technology offers low EMI clock circuitry,

gradual turn-on output drivers (GTOs) and internal Icc

smoothing filters, to help circumvent many of the EMI issues

influencing

embedded

control

designs.

National

has

achieved 15 dB–20 dB reduction in EMI transmissions when

designs have incorporated its patented EMI reducing cir-

cuitry.

6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL

EEPROM

The device includes a program in a boot ROM that provides

the capability, through the MICROWIRE/PLUS serial inter-

face, to erase, program and read the contents of the Flash

memory.

Additional routines are included in the boot ROM, which can

be called by the user program, to enable the user to custom-

ize in-system software update capability if MICROWIRE/

PLUS is not desired.

Additional functions will copy blocks of data between the

RAM and the Flash Memory. These functions provide a

virtual EEPROM capability by allowing the user to emulate a

variable amount of EEPROM by initializing nonvolatile vari-

ables from the Flash Memory and occasionally restoring

these variables to the Flash Memory.

The contents of the boot ROM have been defined by Na-

tional. Execution of code from the boot ROM is dependent

on the state of the FLEX bit in the Option Register on exit

from RESET. If the FLEX bit is a zero, the Flash Memory is

assumed to be empty and execution from the boot ROM

begins. For further information on the FLEX bit, refer to

Section 4.5, Option Register.

6.3 DUAL CLOCK AND CLOCK DOUBLER

The device includes a versatile clocking system and two

oscillator circuits designed to drive a crystal or ceramic

resonator. The primary oscillator operates at high speed up

to 10 MHz.. The secondary oscillator is optimized for opera-

tion at 32.768 kHz.

The user can, through specified transition sequences

(please refer to Section 13.0 Power Saving Features), switch

execution between the high speed and low speed oscillators.

The unused oscillator can then be turned off to minimize

power dissipation. If the low speed oscillator is not used, the

pins are available as general purpose bidirectional ports.

The operation of the CPU will use a clock at twice the

frequency of the selected oscillator (up to 20 MHz for high

speed operation and 65.536 kHz for low speed operation).

This doubled clock will be referred to in this document as

‘MCLK’. The frequency of the selected oscillator will be

referred to as CKI. Instruction execution occurs at one tenth

the selected MCLK rate.

6.4 TRUE IN-SYSTEM EMULATION

On-chip emulation capability has been added, which allows

the user to perform true in-system emulation using final

production boards and devices. This simplifies testing and

evaluation of software in real environmental conditions. The

user, merely by providing for a standard connector which can

be bypassed by jumpers on the final application board, can

provide for software and hardware debugging using actual

production units.

6.5 ARCHITECTURE

The COP8 family is based on a modified Harvard architec-

ture, which allows data tables to be accessed directly from

program memory. This is very important with modern

microcontroller-based applications, since program memory

is usually ROM, EPROM or Flash, while data memory is

usually RAM. Consequently constant data tables need to be

contained in non-volatile memory, so they are not lost when

the microcontroller is powered down. In a modified Harvard

architecture, instruction fetch and memory data transfers

can be overlapped with a two stage pipeline, which allows

the next instruction to be fetched from program memory

while the current instruction is being executed using data

memory. This is not possible with a Von Neumann single-

address bus architecture.

The COP8 family supports a software stack scheme that

allows the user to incorporate many subroutine calls. This

capability is important when using High Level Languages.

With a hardware stack, the user is limited to a small fixed

number of stack levels.

6.6 INSTRUCTION SET

In today’s 8-bit microcontroller application arena cost/

performance, flexibility and time to market are several of the

key issues that system designers face in attempting to build

well-engineered products that compete in the marketplace.

Many of these issues can be addressed through the manner

in which a microcontroller’s instruction set handles process-

ing tasks. And that’s why the COP8 family offers a unique

and code-efficient instruction set - one that provides the

flexibility, functionality, reduced costs and faster time to mar-

ket that today’s microcontroller based products require.

Code efficiency is important because it enables designers to

pack more on-chip functionality into less program memory

space (ROM, OTP or Flash). Selecting a microcontroller with

less program memory size translates into lower system

costs, and the added security of knowing that more code can

be packed into the available program memory space.

6.6.1 Key Instruction Set Features

The COP8 family incorporates a unique combination of in-

struction set features, which provide designers with optimum

code efficiency and program memory utilization.

6.6.2 Single Byte/Single Cycle Code Execution

The efficiency is due to the fact that the majority of instruc-

tions are of the single byte variety, resulting in minimum

program space. Because compact code does not occupy a

substantial amount of program memory space, designers

can integrate additional features and functionality into the

microcontroller program memory space. Also, the majority

instructions executed by the device are single cycle, result-

ing in minimum program execution time. In fact, 77% of the

instructions are single byte single cycle, providing greater

code and I/O efficiency, and faster code execution.

6.6.3 Many Single-Byte, Multi-Function Instructions

The COP8 instruction set utilizes many single-byte, multi-

function instructions. This enables a single instruction to

accomplish multiple functions, such as DRSZ, DCOR, JID,

LD (Load) and X (Exchange) instructions with post-

incrementing and post-decrementing, to name just a few

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