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COP8-REF-AM 数据表(PDF) 43 Page - National Semiconductor (TI) |
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COP8-REF-AM 数据表(HTML) 43 Page - National Semiconductor (TI) |
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43 / 83 page ![]() 14.0 USART (Continued) 14.1 USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. 14.2 DESCRIPTION OF USART REGISTER BITS ENU — USART CONTROL AND STATUS REGISTER (Ad- dress at 0BA) PEN PSEL1 XBIT9/ CHL1 CHL0 ERR RBFL TBMT PSEL0 Bit 7 Bit 0 PEN: This bit enables/disables Parity (7- and 8-bit modes only). Read/Write, cleared on reset. PEN = 0 Parity disabled. PEN = 1 Parity enabled. PSEL1, PSEL0: Parity select bits. Read/Write, cleared on reset. PSEL1 = 0, PSEL0 = 0 Odd Parity (if Parity enabled) PSEL1 = 0, PSEL1 = 1 Even Parity (if Parity enabled) PSEL1 = 1, PSEL0 = 0 Mark(1) (if Parity enabled) PSEL1 = 1, PSEL1 = 1 Space(0) (if Parity enabled) 20006325 FIGURE 21. USART Block Diagram www.national.com 43 |
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