COP8-REF-AM datasheet(33/83 Pages) NSC

33 / 83 page

12.0 Timers (Continued)

the external event occurs. The capture register eliminates

the latency time, thereby allowing the applications program

to retrieve the timer value stored in the capture register.

In this mode, the timer Tx is constantly running at the fixed t

or MCLK rate. The two registers, RxA and RxB, act as

capture registers. Each register also acts in conjunction with

a pin. The register RxA acts in conjunction with the TxA pin

and the register RxB acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin after synchro-

nization to the appropriate internal clock (t

C or MCLK). Con-

trol bits, TxC3, TxC2 and TxC1, allow the trigger events to be

specified either as a positive or a negative edge. The trigger

condition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively latched into the

pending flags, TxPNDA and TxPNDB. The control flag

TxENA allows the interrupt on TxA to be either enabled or

disabled. Setting the TxENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

TxA pin. Similarly, the flag TxENB controls the interrupts

from the TxB pin.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the TxC0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the TxENA control flag. When a TxA interrupt

occurs in the Input Capture mode, the user must check both

the TxPNDA and TxC0 pending flags in order to determine

whether a TxA input capture or a timer underflow (or both)

caused the interrupt.

Figure 17 shows a block diagram of the timer T1 in Input

Capture mode. T2 and T3 are identical to T1.

12.3 TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

TxC3

Timer mode control

TxC2

Timer mode control

TxC1

Timer mode control

TxC0

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in Mode

3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

TxPNDB Timer Interrupt Pending Flag

TxENB

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

The timer mode control bits (TxC3, TxC2 and TxC1) are

detailed in Table 15, Timer Operating Modes.

When the high speed timers are counting in high speed

mode, directly altering the contents of the timer upper or

lower registers, the PWM outputs or the reload registers is

not recommended. Bit operations can be particularly prob-

lematic. Since any of these six registers or the PWM outputs

can change as many as ten times in a single instruction

cycle, performing an SBIT or RBIT operation with the timer

running can produce unpredictable results. The recom-

mended procedure is to stop the timer, perform any changes

to the timer, the PWM outputs or reload register values, and

then re-start the timer. This warning does not apply to the

timer control register. Any type of read/write operation, in-

cluding SBIT and RBIT may be performed on this register in

any operating mode.

20006321

FIGURE 17. Timer in Input Capture Mode

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