COP8-REF-AM datasheet(63/83 Pages) NSC

63 / 83 page

19.0 WATCHDOG/Clock Monitor (Continued)

TABLE 35. WATCHDOG Service Window Select

WDSVR

Bit 7

WDSVR

Bit 6

Clock

Monitor

Bit 0

Service Window

for High Speed Mode

(Lower-Upper Limits)

Service Window

for Dual Clock & Low Speed Modes

(Lower-Upper Limits)

2048-8k t

C Cycles

2048-8k Cycles of 32 kHz Clk

2048-16k t

C Cycles

2048-16k Cycles of 32 kHz Clk

2048-32k t

C Cycles

2048-32k Cycles of 32 kHz Clk

2048-64k t

C Cycles

2048-64k Cycles of 32 kHz Clk

Clock Monitor Disabled

Clock Monitor Enabled

19.1 CLOCK MONITOR

The Clock Monitor aboard the device can be selected or

deselected under program control. The Clock Monitor is

guaranteed not to reject the clock if the instruction cycle

clock (1/t

C) is greater or equal to 5 kHz. This equates to a

clock input rate on the selected oscillator of greater or equal

to 25 kHz.

19.2 WATCHDOG/CLOCK MONITOR OPERATION

The WATCHDOG is enabled by bit 2 of the Option register.

When this Option bit is 0, the WATCHDOG is enabled and

pin G1 becomes the WATCHDOG output with a weak pull-

up.

The WATCHDOG and Clock Monitor are disabled during

reset. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select bits (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR

the WATCHDOG service window (ii) enabling or disabling of

the Clock Monitor. Hence, the first write to WDSVR Register

involves selecting or deselecting the Clock Monitor, select

the WATCHDOG service window and match the WATCH-

DOG key data. Subsequent writes to the WDSVR register

will compare the value being written by the user to the

WATCHDOG service window value, the key data and the

Clock Monitor Enable (all bits) in the WDSVR Register. Table

36 shows the sequence of events that can occur.

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The

WATCHDOG may not be serviced more than once in every

lower limit of the service window.

When jumping to the boot ROM for ISP and virtual E2

operations, the hardware will disable the lower window error

and perform an immediate WATCHDOG service. The ISP

routines will service the WATCHDOG within the selected

upper window. The ISP routines will service the WATCH-

DOG immediately prior to returning execution back to the

user’s code in flash. Therefore, after returning to flash

memory, the user can service the WATCHDOG anytime

following the return from boot ROM, but must service it within

the selected upper window to avoid a WATCHDOG error.

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the port G. WDOUT is active

low. The WDOUT pin has a weak pull-up in the inactive

state. Upon triggering the WATCHDOG, the logic will pull the

WDOUT (G1) pin low for an additional 16–32 cycles after the

signal level on WDOUT pin goes below the lower Schmitt

trigger threshold. After this delay, the device will stop forcing

the WDOUT output low. The WATCHDOG service window

will restart when the WDOUT pin goes high.

A WATCHDOG service while the WDOUT signal is active will

be ignored. The state of the WDOUT pin is not guaranteed

on reset, but if it powers up low then the WATCHDOG will

time out and WDOUT will go high.

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error. The Clock Monitor error will continue

until the clock frequency has reached the minimum specified

value, after which the G1 output will go high following 16–32

clock cycles. The Clock Monitor generates a continual Clock

Monitor error if the oscillator fails to start, or fails to reach the

minimum specified frequency. The specification for the Clock

Monitor is as follows:

1/t

C > 5 kHz — No clock rejection.

1/t

C < 10 Hz — Guaranteed clock rejection.

TABLE 36. WATCHDOG Service Actions

Key Data

Window Data

Clock Monitor

Action

Match

Valid Service: Restart Service Window

Don’t Care

Mismatch

Don’t Care

Error: Generate WATCHDOG Output

Mismatch

Don’t Care

Error: Generate WATCHDOG Output

Don’t Care

Mismatch

Error: Generate WATCHDOG Output

19.3 WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and

CLOCK MONITOR should be noted:

•

Both the WATCHDOG and CLOCK MONITOR detector

circuits are inhibited during RESET.

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