COP8-REF-AM datasheet(45/83 Pages) NSC

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14.0 USART (Continued)

14.4 USART OPERATION

The USART has two modes of operation: asynchronous

mode and synchronous mode.

14.4.1 Asynchronous Mode

This mode is selected by resetting the SSEL (in the ENUI

16 times the baud rate.

The TSFT and TBUF registers double-buffer data for trans-

mission. While TSFT is shifting out the current character on

the TDX pin, the TBUF register may be loaded by software

with the next byte to be transmitted. When TSFT finishes

transmitting the current character the contents of TBUF are

transferred to the TSFT register and the Transmit Buffer

Empty Flag (TBMT in the ENU register) is set. The TBMT

flag is automatically reset by the USART when software

loads a new character into the TBUF register. There is also

the XMTG bit which is set to indicate that the USART is

transmitting. This bit gets reset at the end of the last frame

(end of last Stop bit). TBUF is a read/write register.

The RSFT and RBUF registers double-buffer data being

received. The USART receiver continually monitors the sig-

nal on the RDX pin for a low level to detect the beginning of

a Start bit. Upon sensing this low level, it waits for half a bit

time and samples again. If the RDX pin is still low, the

receiver considers this to be a valid Start bit, and the remain-

ing bits in the character frame are each sampled three times

around the center of the bit time. Serial data input on the

RDX pin is shifted into the RSFT register. Upon receiving the

complete character, the contents of the RSFT register are

copied into the RBUF register and the Received Buffer Full

Flag (RBFL) is set. RBFL is automatically reset when soft-

ware reads the character from the RBUF register. RBUF is a

read only register. There is also the RCVG bit which is set

high when a framing error or break detect occurs and goes

low once RDX goes high.

14.4.2 Synchronous Mode

In this mode data is transferred synchronously with the

clock. Data is transmitted on the rising edge and received on

the falling edge of the synchronous clock.

This mode is selected by setting SSEL bit in the ENUI

the baud rate.

When an external clock input is selected at the CKX pin, data

transmit and receive are performed synchronously with this

clock through TDX/RDX pins.

If data transmit and receive are selected with the CKX pin as

clock output, the device generates the synchronous clock

output at the CKX pin. The internal baud rate generator is

used to produce the synchronous clock. Data transmit and

receive are performed synchronously with this clock.

14.5 FRAMING FORMATS

The USART supports several serial framing formats (Figure

22). The format is selected using control bits in the ENU,

ENUR and ENUI registers.

The first format (1, 1a, 1b, 1c) for data transmission (CHL0 =

1, CHL1 = 0) consists of Start bit, seven Data bits (excluding

parity) and one or two Stop bits. In applications using parity,

the parity bit is generated and verified by hardware.

The second format (CHL0 = 0, CHL1 = 0) consists of one

Start bit, eight Data bits (excluding parity) and one or two

Stop bits. Parity bit is generated and verified by hardware.

The third format for transmission (CHL0 = 0, CHL1 = 1)

consists of one Start bit, nine Data bits and one or two Stop

bits. This format also supports the USART “ATTENTION”

feature. When operating in this format, all eight bits of TBUF

and RBUF are used for data. The ninth data bit is transmitted

and received using two bits in the ENU and ENUR registers,

called XBIT9 and RBIT9. RBIT9 is a read only bit. Parity is

not generated or verified in this mode.

The parity is enabled/disabled by PEN bit located in the ENU

parity is enabled (PEN = 1), the parity selection is then

performed by PSEL0 and PSEL1 bits located in the ENU

Note that the XBIT9/PSEL0 bit located in the ENU register

serves two mutually exclusive functions. This bit programs

the ninth bit for transmission when the USART is operating

with nine data bits per frame. There is no parity selection in

this framing format. For other framing formats XBIT9 is not

needed and the bit is PSEL0 used in conjunction with PSEL1

to select parity.

The frame formats for the receiver differ from the transmitter

in the number of Stop bits required. The receiver only re-

quires one Stop bit in a frame, regardless of the setting of the

Stop bit selection bits in the control register. Note that an

implicit assumption is made for full duplex USART operation

that the framing formats are the same for the transmitter and

receiver.

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