LSM9DS1 datasheet(28/72 Pages) STMICROELECTRONICS

28 / 72 page

Digital interfaces

LSM9DS1

28/72

DocID025715 Rev 3

Digital interfaces

The registers embedded inside the LSM9DS1 may be accessed through both the I2C and

SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire

interface mode.

The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the

CS line must be tied high (i.e connected to Vdd_IO).

5.1

I2C serial interface

The LSM9DS1 I2C is a bus slave. The I2C is employed to write the data to the registers,

whose content can also be read back.

The relevant I2C terminology is provided in the table below.

There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial

DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data

to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-

up resistor. When the bus is free, both the lines are high.

The I2C interface is implemented with fast mode (400 kHz) I2C standards as well as with the

standard mode.

In order to disable the I2C block for accelerometer and gyroscope the I2C_DISABLE bit

must be written to ‘1’ in CTRL_REG9 (23h), while for magnetometer the I2C_DISABLE bit

must be written to ‘1’ in CTRL_REG3_M (22h).

Table 13. Serial interface pin description

Pin name

Pin description

CS_A/G, CS_M

SPI enable

I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI

communication mode / I2C disabled)

SCL/SPC

I2C Serial Clock (SCL)

SPI Serial Port Clock (SPC)

SDA/SDI/SDO

I2C Serial Data (SDA)

SPI Serial Data Input (SDI)

3-wire Interface Serial Data Output (SDO)

SDO_A/G, SDO_M

SPI Serial Data Output (SDO)

I2C less significant bit of the device address

Table 14. I2C terminology

Term

Description

Transmitter

The device which sends data to the bus

Receiver

The device which receives data from the bus

Master

The device which initiates a transfer, generates clock signals and terminates a

transfer

Slave

The device addressed by the master

LSM9DS1 数据表(PDF) 28 Page - STMicroelectronics

LSM9DS1 数据表(HTML) 28 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

数据表下载