FXLS8964AF datasheet(21/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

21 / 98

(CPHA = 0). Single byte read and single byte write operations are completed in 24 SCLK

cycles; multiple byte reads and writes are completed in additional multiples of 8 SCLK

cycles per read or written byte. The first SCLK cycle latches the R/W (Read/Write) bit

to select whether the desired operation is a read (R/W = 1) or a write (R/W = 0). The

following seven SCLK cycles are used to latch the register read or write address.

Note: 4-wire SPI interface mode is the default out of POR or after a soft reset. The 3-wire

interface mode may also be selected by setting

SENS_CONFIG1[SPI_M] = 1.

11.2 SPI write operations with 3- or 4-wire mode

A write operation is initiated by transmitting a 0 for the R/W bit. Then, the 7-bit register

write address, A[6:0], is transmitted in MSb first order. Following this first byte, a second

byte of 0s or 1s (don't care condition) is transferred, followed by the actual data to write

in the third group of 8 SCLK cycles (clock pulses 17 through 24) in MSb first order. The

following figure shows the bus protocol for a single byte register write operation in either

3- or 4-wire SPI mode.

13 14 15 16

R/W A6 A5 A4 A3 A2 A1 A0

18 19

21 22

23 24

D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

SPI_CS_B

SCLK

SPI_MOSI

SPI_MISO

Figure 12. SPI single byte write protocol diagram (3- or 4-wire mode), R/W = 0

Multiple-byte write operations are performed similarly to the single-byte write sequence,

but with additional data bytes transferred over additional 8 SCLK cycle periods. The

clock edge will latch the address for the next register write address. When the desired

number of bytes has been written, a rising edge on the SPI_CS_B pin terminates the

transaction. The following figure shows the bus protocol for multiple byte register write

operations in either 3- or 4-wire SPI mode.

13 14 15 16

R/W A6 A5 A4 A3 A2 A1 A0

18 19

21 22

23 24

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

28 29 30 31 32

High-Impedance

SPI_CS_B

SCLK

SPI_MOSI

SPI_MISO

Figure 13. SPI multiple byte write protocol diagram (3- or 4-wire mode), R/W = 0

11.3 SPI read operations with 4-wire mode

A register read operation is initiated by transmitting a 1 for the R/W bit. Then, the 7-

bit register read address, A[6:0] is encoded in the first byte. Following this first byte, a

second byte of 0s or 1s (don't care condition) is transferred. After this transfer completes,

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