FXLS8964AF datasheet(39/98 Pages) NXP

39 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

39 / 98

Field

Description

SRC_BOOT

System boot complete event flag

0: Boot sequence in process/not complete.

1: Boot sequence completed; FXLS8964AF is now ready to accept commands over the I2C or SPI

interfaces.

This flag is automatically set to 1 upon completion of the boot process and remains set until a POR,

soft reset, or exit from Hibernate mode event occurs.

When BT_MODE = GND: Boot interrupt is generated in INT1/MOT_DET pin by default. This event

flag may be configured to generate an interrupt on either the INT1 or INT2 pin depending on the

mapping selected in

INT_PIN_SEL. When this event flag is enabled as an interrupt output, either the

INT1 or INT2 (depending on the setting made in

INT_PIN_SEL register) pin is pulsed once with a

width of TBOOT1 µs when the boot process completes.

When BT_MODE = VDD: The INT2/BOOT_OUT pin is pulsed once with a duration of TBOOT2 ms when

the boot process completes. The pulse is active low (open-drain output); an external pull-up resistor is

required.

Notes:

• When BT_MODE = GND, after a POR or exiting Hibernate mode, the polarity of the BOOT pulse

will be default Active High because any I2C write to the

SENS_CONFIG4[INT_POL] will fail until the

boot process has completed.

• After a Soft Reset, the INT_POL, INT_PP_OD, and INT_PIN_SEL register settings are

not reset and maintain their previous values. As a result, an I2C or SPI write to the

SENS_

CONFIG4[(INT_PP_OD and INT_POL bits)] and INT_PIN_SEL[BOOT_INT2] bits before the

Soft Reset will determine the logic polarity, output driver type, and INT1/2 pin mapping of the

subsequent Boot pulse.

• It is not possible to observe the state of the SRC_BOOT bit at '0' over the I2C or SPI interfaces as

read and write operations will fail until the boot process has completed.

13.2 TEMP_OUT register (address 01h)

Table 22. TEMP_OUT register (address 01h) bit allocation

Bit

Name

TEMP_OUT[7:0]

Reset

—

Access

The

TEMP_OUT register contains the 8-bit, 2's complement temperature value. When

this register contains the value 00h, the measured temperature is 25 °C (typ). This

13.3 VECM_LSB register (address 02h)

This register contains the LSB of the 12-bit, unsigned vector magnitude

result (acceleration vector modulus); The result is only calculated when

SENS_CONFIG5[VECM_EN] = 1. Note that whenever the VECM_LSB or VECM_MSB

registers are read the SRC_DRDY event flag is also cleared. The endianness of the

vector magnitude output data is programmable via SENS_CONFIG2[LE_BE] and

defaults to little-endian mode.

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