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FXLS8964AF 数据表(PDF) 64 Page - NXP Semiconductors |
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FXLS8964AF 数据表(HTML) 64 Page - NXP Semiconductors |
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64 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 64 / 98 Table 73. INT_PIN_SEL register (address 21h) bit description Field Description 7 DRDY_INT2 Data-ready interrupt routing 0: Interrupt signal is routed to INT1 pin if it is enabled. 1: Interrupt signal is routed to INT2 pin if it is enabled. 6 BUF_INT2 Output buffer interrupt routing ( BUF_OVF | BUF_WMRK | BUF_GATE_ERR): 0: Interrupt signal is routed to INT1 pin if it is enabled. (default) 1: Interrupt signal is routed to INT2 pin if it is enabled. 5 SDCD_OT_INT2 SDCD outside of thresholds event interrupt routing 0: Interrupt signal is routed to INT1 pin if it is enabled. 1: Interrupt signal is routed to INT2 pin if it is enabled. 4 SDCD_WT_INT2 SDCD within thresholds event interrupt routing 0: Interrupt signal is routed to INT1 pin if it is enabled. 1: Interrupt signal is routed to INT2 pin if it is enabled. 3 ORIENT_INT2 ORIENT event interrupt routing 0: Interrupt signal is routed to INT1 pin if it is enabled. 1: Interrupt signal is routed to INT2 pin if it is enabled. 2 ASLP_INT2 Auto-WAKE/SLEEP event interrupt routing 0: Interrupt signal is routed to INT1 pin if it is enabled. 1: Interrupt signal is routed to INT2 pin if it is enabled. 1 BOOT_INT2 BOOT event interrupt routing If a user operation sets BOOT_INT2 before issuing a soft reset command, the setting is maintained through the reset sequence (the setting is lost if VDD supply is removed). 0: Interrupt signal is routed to INT1 pin if it is enabled. 1: Interrupt signal is routed to INT2 pin if it is enabled. Note: When BT_MODE = VDD, this bit is ignored; the BOOT interrupt is internally mapped to the INT2/BOOT_OUT pin (fixed setting). 0 WAKE_OUT_INT2 WAKE power state interrupt routing 0: WAKE power state output is routed to INT1 pin if it is enabled. 1: WAKE power state output is routed to INT2 pin if it is enabled. 13.23 OFF_X, OFF_Y, OFF_Z registers (addresses 22h to 24h) Registers 22h to 24h (OFF_X/Y/Z) can be used to realign the zero-g position of the X-, Y- and Z-axes after PCB assembly. The registers are 8 bit, 2's complement providing an offset adjustment range of –128 to 127. The effective offset value in mg set by each of the OFF_X/Y/Z registers is determined by the following equation (example for the X-axis, with the other axes offsets set in an identical manner): OFF_X For example, writing the value +16 (10h) into the OFF_X register in the ±4 g FSR results in an effective X-axis offset of 16 LSB * 2 * 1.95 mg/LSB = 62.4 mg. |
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