FXLS8964AF datasheet(49/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

49 / 98

Field

Description

1:0

SYS_MODE[1:0]

The current system operating mode

00b: Standby mode (default mode after a POR or soft reset event when BT_MODE = GND)

01b: WAKE mode (default mode after a POR or soft reset event when BT_MODE = VDD and

MOT_DET = 1)

10b: SLEEP mode

11b: EXT_TRIG mode (this mode is unavailable when BT_MODE = VDD)

Notes:

• When external trigger mode is enabled (with SENS_CONFIG4[INT2_FUNC] = 1), while the

device is waiting for a trigger event to occur, SYS_MODE[1:0] will be set to 11b. When the

trigger is received, SYS_MODE[1:0] will be set to 01b while the measurement is being made,

and then change back to 11b and remain there until the next trigger signal is received.

• When INT_EN[WAKE_OUT_EN] = 1, and SYS_MODE[1:0] = 01b (WAKE), the device will

output either a logic '1' or '0' on either the INT1 or INT2 pins, depending on the settings made in

INT_PIN_SEL[WAKE_OUT_INT2] and SENS_CONFIG4[INT_POL].

• When entering the WAKE, SLEEP, or EXT_TRIG modes, the internal debounce counters for

the ORIENT, SDCD_WT, and SDCD_OT event functions are automatically reset.

13.11 SENS_CONFIG1 register (address 15h)

Table 46. SENS_CONFIG1 register (address 15h) bit allocation

Bit

Name

RST

ST_AXIS_SEL[1:0]

ST_POL

SPI_M

FSR[1:0]

ACTIVE

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 47. SENS_CONFIG1 register (address 15h) bit description

Field

Description

RST

The RST bit may be used to initiate a software reset. The reset mechanism can be triggered in

Standby, Active (WAKE or SLEEP), and EXT_TRIG operating modes. When the RST bit is set, the

boot mechanism resets all functional blocks and loads the internal registers with their default values

(The

INT_POL, INT_PP_OD, and BOOT_DIS bits are not reset and will maintain their current values

as long as power is not removed from the VDD pin and Hibernate mode is not enabled). The host

application should allow TBOOT1 or TBOOT2 ms between issuing a reset command and attempting

communications with FXLS8964AF over the I2C/SPI interfaces. Alternatively, the host can wait for the

active edge on the TBOOT1/2 pulse event signaled on the configured INTx pin.

0: No device reset pending

1: Write '1' to trigger the soft reset sequence

Notes:

• The I2C and SPI interface blocks are also reset to avoid corrupted data transactions.

• The reset sequence will not start until the host I2C controller issues the SP (stop) condition, or the

SPI master releases the SPI_CS_B pin.

• The host will always read back this bit as '0'.

• There is a delay of 300 μs to 500 μs between setting the RST bit and the commencement of the

reset sequence.

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