FXLS8964AF datasheet(5/98 Pages) NXP

5 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2 — 30 October 2020

5 / 98

Symbol

Description

SPI_CS_B / WAKE_UP

SPI chip select input, active low / Hibernate mode Wake-Up pin.[6] The

WAKE_UP function is only available when BT_MODE = GND.

INT1 / MOT_DET

Mode dependent multifunction I/O pin 1.[7]

BT_MODE = GND: Programmable interrupt output pin 1.[5] This pin should

be left unconnected if unused in the application circuit.

BT_MODE = VDD: MOT_DET multifunction I/O.[4] The host MCU sets this

pin high through a pull-up resistor to enable motion detection, and drives

it low for greater than TMOT-HIB ms to disable motion detection and enter

Hibernate mode. FXLS8964AF will pulse the line low for TPULSE-MOT ms

after motion is detected. This line may also be used to select the motion

detection threshold. See Section 12 for more information.

INTF_SEL

Device interface mode selection pin.

VDD: SPI interface mode [3]

GND: I2C interface mode

GND

Supply return connection.

[1]

BT_MODE state is latched after POR.

[2]

Under Hibernate mode, pin configuration is High Impedance.

[3]

3-wire SPI mode may be selected in

SENS_CONFIG1[SPI_M]; 3-wire operation is also possible by directly connecting the SPI_MISO and SPI_MOSI pins

together on the PCB.

[4]

An external pull-up resistor is required on this pin when BT_MODE = VDD.

[5]

This pin is configurable as either an input or output (push-pull or open-drain/open-source output type), but defaults to a push-pull output after POR, or after

exiting Hibernate mode.

[6]

Under Hibernate mode, pin configuration is High Impedance (when BT_MODE = VDD) and CMOS Input (when BT_MODE = GND).

[7]

Under Hibernate mode, pin configuration is High Impedance (when BT_MODE = GND) and CMOS Input (when BT_MODE = VDD).

7 System connections

FXLS8964AF connects to a host processor through an I2C or SPI interface. Figure 3 to

Figure 8 show the recommended circuit connections.

7.1 Typical application circuits

X7R or X5R ceramic capacitors are recommended for VDD supply decoupling. A 1 µF

capacitor in parallel with a 0.1 µF is recommended as a starting point per NXP's EMC

test standard. These capacitors should be placed as close to the VDD supply pin as

practical. The values of the capacitors can be changed to suit the application's EMC

performance requirements.

VDD

SA0/SPI_MISO

BT_MODE

SCL/SCLK

GND

INTF_SEL

INT1/MOT_DET

SPI_CS_B/WAKE_UP

INT2/EXT_TRIG/BOOT_OUT

SDA/SPI_MOSI

0.1

1.0 µF

VDD

INT1

I2C_SDA

I2C_SCL

VDD

I2C_SA0

INT2/EXT_TRIG

WAKE_UP

µF

Figure 3. Typical Application Circuit #1 – I2C mode

FXLS8964AF 数据表(PDF) 5 Page - NXP Semiconductors

FXLS8964AF 数据表(HTML) 5 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

数据表下载