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FXLS8964AF 数据表(PDF) 55 Page - NXP Semiconductors

部件名 FXLS8964AF
功能描述  3-Axis Low-g Accelerometer
PDF  98 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

FXLS8964AF 数据表(HTML) 55 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8964AF
3-Axis Low-g Accelerometer
FXLS8964AF
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Objective data sheet
Rev. 2 — 30 October 2020
55 / 98
13.14 SENS_CONFIG4 register (address 18h)
Table 54. SENS_CONFIG4 register (address 18h) bit allocation
Bit
7
6
5
4
3
2
1
0
Name
EXT_
TRIG_M
WAKE_
SDCD_WT
WAKE_
SDCD_OT
WAKE_
ORIENT
DRDY_PUL INT2_FUNC
INT_
PP_OD
INT_POL
Reset
0
0
0
0
0
0
0
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 55. SENS_CONFIG4 register (address 18h) bit description
Field
Description
7
EXT_TRIG_M
External trigger function acquisition mode.
0 (default): Each positive going trigger edge causes a single ADC acquisition to be made. When
the number of acquisitions specified by the current operating mode decimation setting have been
triggered, the final decimated output is stored in the
OUT_X/Y/Z registers or the buffer depending on
the setting made in
BUF_CONFIG1[BUF_MODE[1:0]]. .
1: Each positive going trigger edge causes the number of acquisitions specified by the current
operating mode decimation setting to be automatically made (only one trigger event is needed to
acquire all of the measurements specified by the decimation setting). Once the specified number of
acquisitions have been made, the final decimated output is stored in the
OUT_X/Y/Z registers or the
buffer depending on the setting made in
BUF_CONFIG1[BUF_MODE[1:0]].
Notes:
• The EXT_TRIG_M setting only applies when INT2_FUNC = 1.
• The SRC_DRDY event flag is asserted after the specified number of measurements have
completed and the final decimated output result is available. Note that the SRC_DRDY flag is only
asserted when
BUF_CONFIG1[BUF_MODE[1:0]] = 00b
• In LPM, this bit has no effect as the decimation factor is fixed at 1.
6
WAKE_SDCD_WT
SDCD within thresholds event Auto-WAKE/SLEEP transition source enable
0 (default): SDCD within thresholds event is not used to prevent entry into/trigger an exit from SLEEP
mode.
1: SDCD within thresholds event is used to prevent entry into/trigger an exit from SLEEP mode.
5
WAKE_SDCD_OT
SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable
0 (default): SDCD outside of thresholds event is not used to prevent entry into/trigger an exit from
SLEEP mode.
1: SDCD outside of thresholds event is used to prevent entry into/trigger an exit from SLEEP mode.
4
WAKE_ORIENT
Orientation change event Auto-WAKE/SLEEP transition source enable
0 (default): Orientation change condition is not used as an event to prevent entry into /trigger an exit
from SLEEP mode.
1: Orientation change condition is used as an event to prevent entry into/trigger an exit from SLEEP
mode.
3
DRDY_PUL
Pulse generation option for DRDY event
0 (default): A SRC_DRDY event is output on the INTx pin as an active high or active low signal
depending on the polarity setting made in INT_POL. The INTx pin will remain asserted until the host
reads any of the OUT_X/Y/Z registers.
1: A 32 μs (nominal) duration pulse is output on the configured INTx pin once per ODR cycle. The
output pulse is either positive or negative, depending on the INT_POL setting. Note: The pulsed
output signal is OR'd with all of the other interrupt events assigned to the INTx pin. Note: In Motion
Detection mode (BT_MODE = VDD), the state of this bit is ignored and has no effect on device
operation.



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