FXLS8964AF datasheet(35/98 Pages) NXP

35 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

35 / 98

Auto-increment Address

Name

Type

Address

F_READ = 0

F_READ = 1

Default

Values

BT_MODE =

GND/[VDD]

Comment

SENS_CONFIG1 [1] [5]

R/W

15h

16h

00h/[03h]

Full-scale range selection, Self-Test axis and

polarity selection, soft reset, Active mode

enable.

SENS_CONFIG2 [1] [5]

R/W

16h

17h

00h

WAKE and SLEEP power mode selections,

little/big endian output mode, auto-increment

control, fast read enable.

SENS_CONFIG3 [1] [5]

R/W

17h

18h

00h/[C0h]

WAKE and SLEEP mode ODR and decimation

selections

SENS_CONFIG4 [1] [5]

R/W

18h

19h

01h

Auto-WAKE/SLEEP interrupt source enable

bits, interrupt output pin logic polarity and

driver type, external trigger input function

enable

SENS_CONFIG5 [1] [5]

R/W

19h

1Ah

00h/[00h]

Auto-increment mechanism disable bits for X/

Y/Z axis data; Hibernate mode enable

WAKE_IDLE _LSB [1] [5]

R/W

1Ah

1Bh

00h

LSB of 12-bit user programmable WAKE mode

idle time - wake_idle[7:0]

WAKE_IDLE_MSB [1] [5]

R/W

1Bh

1Ch

00h

MSB of 12-bit user programmable WAKE

mode idle time - wake_idle[11:8]

SLEEP_IDLE_LSB [1] [5]

R/W

1Ch

1Dh

00h

LSB of 12-bit user programmable SLEEP

mode idle time - sleep_idle[7:0]

SLEEP_IDLE_MSB [1] [5]

R/W

1Dh

1Eh

00h

MSB of 12-bit user programmable SLEEP

mode idle time - sleep_idle[11:8]

ASLP_COUNT_LSB [1] [5]

R/W

1Eh

1Fh

00h

LSB of inactivity time-out count value used for

transitioning into Auto-SLEEP mode: aslp_

count[7:0]. In order to enable the Auto-WAKE/

SLEEP feature the value written to this register

must be ≥ 1.

ASLP_COUNT_MSB [1] [5]

R/W

1Fh

20h

00h

MSB of inactivity time-out count value used

for transitioning into Auto-SLEEP mode: aslp_

count[11:8]

INT_EN [1] [5]

R/W

20h

21h

00h/[20h]

Interrupt output enable register

INT_PIN_SEL [1] [5]

R/W

21h

22h

00h

Interrupt output routing register (INT1, INT2

pins)

Zero-g offset compensation registers

OFF_X [1] [5]

R/W

22h

23h

00h

X-Axis acceleration zero-g offset: x_off[7:0]

OFF_Y [1] [5]

R/W

23h

24h

00h

Y-Axis acceleration zero-g offset: y_off[7:0]

OFF_Z [1] [5]

R/W

24h

25h

00h

Z-Axis acceleration zero-g offset: z_off[7:0]

Output Buffer Configuration

RESERVED_REG2

—

25h

26h

00h

Factory reserved register address 2

BUF_CONFIG1 [1] [5]

R/W

26h

27h

00h

Output data buffer operating mode, trigger

source selection, and data collection mode.

BUF_CONFIG2 [1] [5]

R/W

27h

28h

00h

Output data buffer flush, gate control and

watermark level (buf_wmrk[5:0]).

*The BUF_FLUSH bit may be set at any time

in either STANDBY, ACTIVE, OR EXT_TRIG

modes.

Orientation detection function configuration and status

ORIENT_STATUS [1] [2]

28h

29h

00h

Orientation event status

ORIENT_CONFIG [1] [5]

R/W

29h

2Ah

80h

Orientation detection function configuration.

ORIENT_DBCOUNT [1] [5]

R/W

2Ah

2Bh

00h

Orientation detection change debounce

counter

ORIENT_BF_ZCOMP [1] [5]

R/W

2Bh

2Ch

44h

Back/Front orientation state change threshold

angle.

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