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FXLS8964AF 数据表(PDF) 82 Page - NXP Semiconductors |
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FXLS8964AF 数据表(HTML) 82 Page - NXP Semiconductors |
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82 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 82 / 98 SDCD_UTHS[11:0] to ensure that the SDCD circuit functions correctly and produces meaningful results. The scaling for this register is always the same as the selected FSR's sensitivity. See Section 9.4 for the sensitivity values corresponding to each of the selectable FSRs. Table 109. SDCD_LTHS_MSB register (address 34h) bit allocation Bit 7 6 5 4 3 2 1 0 Name — — — — SDCD_LTHS[11:8] Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 0 0 0 0 1 1 1 1 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 110. SDCD_LTHS_MSB register (address 34h) bit description Field Description 3:0 SDCD_LTHS[11:8] MSB (nibble) of the signed 12-bit 2's complement lower-threshold value 13.31.9 SDCD_UTHS_LSB register (address 35h) Sensor Data Change Detection function 12-bit 2's complement upper-threshold least-significant byte. SDCD_UTHS[11:0] must always be set to a higher value than SDCD_LTHS[11:0] to ensure that the SDCD circuit functions correctly and produces meaningful results. The scaling for this register is the same as the selected FSR sensitivity. See Section 9.4 for the sensitivity values corresponding to each of the selectable FSRs. Table 111. SDCD_UTHS_LSB register (address 35h) bit allocation Bit 7 6 5 4 3 2 1 0 Name SDCD_UTHS[7:0] Reset (BT_MODE = GND) 0 0 0 0 0 0 0 0 Reset (BT_MODE = VDD) 0 1 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 112. SDCD_UTHS_LSB register (address 35h) bit description Field Description 7:0 SDCD_UTHS[7:0] LSB of the signed 12 bit 2's complement upper-threshold value 13.31.10 SDCD_UTHS_MSB register (address 36h) Sensor Data Change Detection function 12-bit 2's complement upper-threshold most- significant byte (nibble). SDCD_UTHS[11:0] must always be set to a higher value than SDCD_LTHS[11:0] to ensure that the SDCD circuit functions correctly and produces meaningful results. |
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