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FXLS8964AF 数据表(PDF) 74 Page - NXP Semiconductors |
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FXLS8964AF 数据表(HTML) 74 Page - NXP Semiconductors |
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74 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Objective data sheet Rev. 2 — 30 October 2020 74 / 98 1 0 WINDOW COMPARATOR SDCD_UTHS[11:0] SDCD_LTHS[11:0] OUT_X[n], OUT_Y[n], OUT_Z[n] X_OT_EN Y_OT_EN Z_OT_EN X_OT Y_OT Z_OT X_WT_EN Y_WT_EN Z_WT_EN OT_DBCTM REF_X[n], REF_Y[n], REF_Z[n] REF_UPDM[1:0] X_POL Y_POL Z_POL X_WT_EF Y_WT_EF Z_WT_EF X_WT_EN Y_WT_EN WT_LOG_SEL WT_ELE WT_EA aaa-027616 OT_EA X_OT_EF_POL Y_OT_EF_POL Z_OT_EF_POL SDCD_OT_DBCNT[7:0] WT_DBCTM SDCD_WT_DBCNT[7:0] Y_OT_EF Z_OT_EF X_OT_EF X_WT_EF Y_WT_EF Z_WT_EF X_WT_EF Y_WT_EF Z_WT_EF SDCD_EN 11 01 00 10 OT_ELE WT_ELE Z_WT_EN MUX VECM[n] MODE SATURATOR Z_OT_DBCNT_INT[7:0] W_DBCNT_INT[7:0] Y_OT_DBCNT_INT[7:0] X_OT_DBCNT_INT[7:0] LATCH LATCH LATCH LATCH LATCH LATCH LATCH LATCH 12 12 12 12 12 12 12 12 12 12 13 2 12 X_WT_EF Y_WT_EF Z_WT_EF X_WT_EN Y_WT_EN Z_WT_EN Figure 23. SDCD Function Block Diagram 13.31.1 SDCD_INT_SRC1 register (address 2Dh) This register contains the SDCD outside-of-thresholds event status flags. The OT_EA flag may be used to signal interrupts to a host processor if mapped to one of the INT1 or INT2 pins. Table 95. SDCD_INT_SRC1 register (address 2Dh) bit allocation Bit 7 6 5 4 3 2 1 0 Name OT_EA — X_OT_EF X_OT_POL Y_OT_EF Y_OT_POL Z_OT_EF Z_OT_POL Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R |
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