FXLS8964AF datasheet(23/98 Pages) NXP

23 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

23 / 98

13 14 15 16

R/W A6 A5 A4 A3 A2 A1 A0

18 19

21 22

23 24

D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

SPI_CS_B

SCLK

SPI_DATA

SPI_MISO

Figure 16. SPI single byte read protocol diagram (3-wire mode)

13 14 15 16

R/W A6 A5 A4 A3 A2 A1 A0

18 19

21 22

23 24

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

28 29 30 31 32

High-Impedance

SPI_DATA

SPI_CS_B

SCLK

SPI_MISO

Figure 17. SPI multiple byte read protocol diagram (3-wire mode)

11.5 SPI timing specifications (4-wire mode and 3-wire hardwired modes)

Table 12 and Figure 18 specify and illustrate the minimum and maximum timing

parameter values for correct SPI interface functionality when FXLS8964AF is operated

in 4-wire and 3-wire hardwired SPI modes. FXLS8964AF only supports SPI mode

00, corresponding to CPOL = 0, and CPHA = 0. In this mode, the active state of the

clock is high and the idle state is low. Data is latched on the rising edge of the clock

and propagated on the falling edge. All timing specifications shown in Table 12 were

determined under the following conditions: 10 pF capacitor and 1 kΩ pull-up resistor

present on all SPI signals, 105 °C, 1.8 V.

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