MCP47FVB01 datasheet(22/92 Pages) MICROCHIP

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MCP47FVBXX

DS20005405A-page 22

 2015 Microchip Technology Inc.

TABLE 1-5:

I2C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED)

I2C™ AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40

C  TA  +125C (Extended)

Operating Voltage range is described in DC Characteristics

Param.

No.

Sym.

Characteristic

Min.

Max.

Units

Conditions

103A(2)

TFSCL

SCL fall time

100 kHz mode

—

300

Cb is specified to be from

10 to 400 pF

(100 pF maximum for

3.4 MHz mode)(4)

400 kHz mode

20 + 0.1Cb

300

1.7 MHz mode

3.4 MHz mode

103B (2)

TFSDA

SDA fall time

100 kHz mode

—

300

Cb is specified to be from

10 to 400 pF

(100 pF maximum for

3.4 MHz mode)(4)

400 kHz mode

20 + 0.1Cb

300

1.7 MHz mode

160

3.4 MHz mode

106

THD:DAT Data input hold

time

100 kHz mode

—

1.8V-5.5V(2, 5)

400 kHz mode

—

2.7V-5.5V(5)

1.7 MHz mode

—

4.5V-5.5V(5)

3.4 MHz mode

—

4.5V-5.5V(5)

107

TSU:DAT Data input

setup time

100 kHz mode

250

—

Note 2

, Note 6

400 kHz mode

100

—

Note 6

1.7 MHz mode

—

3.4 MHz mode

—

109

TAA

Output valid

from clock

100 kHz mode

—

3450

Note 2

, Note 7

400 kHz mode

—

900

Note 7

1.7 MHz mode

—

150

Cb = 100 pF(7, 8)

—310

Cb = 400 pF(2, 7)

3.4 MHz mode

—

150

Cb = 100 pF(7)

110

TBUF

Bus free time

100 kHz mode

4700

—

Time the bus must be free

before a new transmis-

sion can start(2)

400 kHz mode

1300

—

1.7 MHz mode

N.A.

—

3.4 MHz mode

N.A.

—

111

TSP

Input filter spike

suppression

(SDA and SCL)

100 kHz mode

—

NXP Spec states N.A.(2)

400 kHz mode

—

1.7 MHz mode

—

Spike suppression

3.4 MHz mode

—

Spike suppression

Note 2

Not Tested. This parameter ensured by characterization.

Note 4

Use Cb in pF for the calculations.

Note 5

A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

Note 6

A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the

requirement tSU;DAT  250 ns must then be met. This will automatically be the case if the device does not

stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it

must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the

standard-mode I2C bus specification) before the SCL line is released.

Note 7

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

Note 8

Ensured by the TAA 3.4 MHz specification test.

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