MCP47FVB01 datasheet(47/92 Pages) MICROCHIP

47 / 92 page

 2015 Microchip Technology Inc.

DS20005405A-page 47

MCP47FVBXX

5.6.1

EXITING POWER-DOWN

When the device exits the power-down mode the

following occurs:

• Disabled circuits (op amp, resistor ladder, ...) are

turned on

• Resistor ladder is connected to selected

reference voltage (VRL)

• Selected pull-down resistor is disconnected

•The VOUT output will be driven to the voltage

represented by the volatile DAC register’s value

and configuration bits

The VOUT output signal will require time as these

circuits are powered-up and the output voltage is driven

to the specified value as determined by the volatile

DAC register and configuration bits.

The following events will change the PD1:PD0 bits to ‘00’

and therefore exit the Power-Down mode. These are:

•Any I2C write command where the PD1:PD0 bits

are ‘00’

•I2C General Call Wake-up Command

•I2C General Call Reset Command.

5.6.2

RESET COMMANDS

When the MCP47FVBXX is in the valid operating volt-

age, the I2C General Call Reset command will force a

Reset event. This is similar to the Power-on Reset,

except that the Reset delay timer is not started.

If the I2C interface bus does not seem to be respon-

sive, the technique shown in Section 8.9 “Software

I2C Interface Reset Sequence”

can be used to force the

I2C interface to be reset.

5.7

DAC Registers, Configuration

Bits, and Status Bits

The MCP47FVBXX devices have volatile memory.

Table 4-2 shows the volatile and the interaction due to

a POR event.

There are five configuration bits in the volatile memory,

the DAC registers in the volatile memory and two vola-

tile status bits. The volatile DAC registers will be either

12-bits (MCP47FVB2X), 10-bits (MCP47FVB1X), or 8-

bits (MCP47FVB0X) wide.

When the device is first powered-up, it automatically

forces the device default values to the volatile memory.

The volatile memory determines the analog output

(VOUT) pin voltage. After the device is powered-up, the

user can update the device memory.

The I2C interface is how this memory is read and written.

Refer to Section 6.0 “I2C Serial Interface Module” and

Section 7.0 “Device Commands”

for more details on

reading and writing the device’s memory.

bits and Table 4-2 shows the factory default value of a

POR/BOR event for the device configuration bits.

There is one status bit (the POR bit) and it indicates if

the device VDD is above or below the POR trip point.

After a POR event, this bit is a ‘1’, reading the Gain

Control and System Status register clears this bit (‘0’).

Note:

Since the op amp and resistor ladder were

powered-off (0V), the op amp’s input

voltage (VW) can be considered 0V. There

is a delay (TPDD) between the PD1:PD0

bits updating to ‘00’ and the op amp driv-

ing the VOUT output. The op amp’s settling

time (from 0V) needs to be taken into

account to ensure the VOUT voltage

reflects the selected value.

MCP47FVB01 数据表(PDF) 47 Page - Microchip Technology

MCP47FVB01 数据表(HTML) 47 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载