MCP47FVB01 datasheet(79/92 Pages) MICROCHIP

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DS20005405A-page 79

MCP47FVBXX

B.2

Signal Descriptions

The I2C interface uses two pins (signals). These are:

• SDA (Serial Data)

• SCL (Serial Clock)

B.2.1

SERIAL DATA (SDA)

The Serial Data (SDA) signal is the data signal of the

device. The value on this pin is latched on the rising

edge of the SCL signal when the signal is an input.

With the exception of the Start (Restart) and Stop con-

ditions, the high or low state of the SDA pin can only

change when the clock signal on the SCL pin is low.

During the high period of the clock, the SDA pin’s value

(high or low) must be stable. Changes in the SDA pin’s

value while the SCL pin is high will be interpreted as a

Start or a Stop condition.

B.2.2

SERIAL CLOCK (SCL)

The Serial Clock (SCL) signal is the clock signal of the

device. The rising edge of the SCL signal latches the

value on the SDA pin.

Depending on the clock rate mode, the interface will

display different characteristics.

B.3

I2C Operation

B.3.1

I2C BIT STATES AND SEQUENCE

Figure B-8 shows the I2C transfer sequence, while

Figure B-7 shows the bit definitions. The serial clock is

generated by the master. The following definitions are

used for the bit states:

• Start Bit (S)

• Data Bit

• Acknowledge (A) Bit (driven low) /

No Acknowledge (A) bit (not driven low)

• Repeated Start Bit (Sr)

• Stop Bit (P)

B.3.1.1

Start Bit

The Start bit (see Figure B-2) indicates the beginning of

a data transfer sequence. The Start bit is defined as the

SDA signal falling when the SCL signal is “high”.

FIGURE B-2:

Start Bit.

B.3.1.2

Data Bit

The SDA signal may change state while the SCL signal

is low. While the SCL signal is high, the SDA signal

MUST be stable (see Figure B-3).

FIGURE B-3:

Data Bit.

B.3.1.3

Acknowledge (A) Bit

The A bit (see Figure B-4) is typically a response from

the receiving device to the transmitting device.

Depending on the context of the transfer sequence, the

A bit may indicate different things. Typically, the slave

device will supply an A response after the Start bit and

8 “data” bits have been received. An A bit has the SDA

signal low, while the A bit has the SDA signal high.

FIGURE B-4:

Acknowledge Waveform.

Table B-1 shows some of the conditions where the

slave device issues the A or Not A (A).

If an error condition occurs (such as an A instead of A),

then a Start bit must be issued to reset the command

state machine.

SDA

SCL

1st Bit

2nd Bit

TABLE B-1:

MCP47FVBXX A/A

RESPONSES

Event

Acknowledge

Bit Response

Comment

General Call

Slave Address

valid

Slave Address

not valid

Bus Collision

N/A

I2C™ module

Resets, or a “Don’t

Care” if the colli-

sion occurs on the

Master’s “Start bit”

SDA

SCL

Data Bit

1st Bit

2nd Bit

SDA

SCL

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