MCP47FVB01 datasheet(29/92 Pages) MICROCHIP

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DS20005405A-page 29

MCP47FVBXX

4.0

GENERAL DESCRIPTION

The MCP47FVBX1 (MCP47FVB01, MCP47FVB11,

and MCP47FVB21) devices are single-channel voltage

output

devices.

MCP47FVBX2

(MCP47FVB02,

MCP47FVB12, and MCP47FVB22) devices are dual-

channel voltage output devices.

These devices are offered with 8-bit (MCP47FVB0X),

10-bit (MCP47FVB1X) and 12-bit (MCP47FVB2X)

resolution and include an I2C serial interface and a

write latch (LAT) pin to control the update of the written

DAC value to the DAC output pin.

The devices use a resistor ladder architecture. The

resistor ladder DAC is driven from a software-

selectable voltage reference source. The source can

be either the device’s internal VDD, an external VREF

pin voltage (buffered or unbuffered) or an internal band

gap voltage source.

The DAC output is buffered with a low power and

precision output amplifier (op amp). This output

amplifier provides a rail-to-rail output with low offset

voltage and low noise. The gain (1x or 2x) of the

output buffer is software configurable.

The devices operates from a single supply voltage.

This voltage is specified from 2.7V to 5.5V for full

specified operation, and from 1.8V to 5.5V for digital

operation. The device operates between 1.8V and

2.7V, but some device parameters are not specified.

The main functional blocks are:

• Power-on Reset/Brown-out Reset (POR/BOR)

• Device Memory

• Resistor Ladder

• Output Buffer/VOUT Operation

• Internal Band Gap (Voltage Reference)

•I2C Serial Interface Module

4.1

Power-on Reset/Brown-out Reset

(POR/BOR)

The internal Power-on Reset (POR)/Brown-out Reset

(BOR) circuit monitors the power supply voltage (VDD)

during operation. This circuit ensures correct device

start-up at system power-up and power-down events.

The device’s RAM retention voltage (VRAM) is lower

than the POR/BOR voltage trip point (VPOR/VBOR).

The maximum VPOR/VBOR voltage is less than 1.8V.

POR occurs as the voltage is rising (typically from 0V),

while BOR occurs as the voltage is falling (typically

from VDD(MIN) or higher).

The POR and BOR trip points are at the same voltage,

and the condition is determined by whether the VDD

voltage is rising or falling (see Figure 4-1). What occurs is

different depending on if the reset is a POR or BOR reset.

When

VPOR/VBOR <VDD < 1.8V,

the

electrical

performance

may

not

meet

the

data

sheet

specifications. In this region, the device is capable of

reading and writing to its volatile memory if the proper

serial command is executed.

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